* config/mips/mips.md (*lowsi): Renamed from lowsi.

	(*lowdi): Likewise lowdi.
	(*lowsi_mips16, *lowdi_mips16): New patterns.
	* config/mips/mips.c (mips_const_insns, mips_output_move): Remove
	mips16 CONSTANT_RELOC handling.
	(mips_delegitimize_address): Adjust for new sdata representation.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@72157 138bc75d-0d04-0410-961f-82ee72b054a4

3 files changed, 40 insertions, 14 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5e01a062a6d..681f6776af3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,14 @@
 2003-10-06  Richard Sandiford  <rsandifo@redhat.com>
 
+	* config/mips/mips.md (*lowsi): Renamed from lowsi.
+	(*lowdi): Likewise lowdi.
+	(*lowsi_mips16, *lowdi_mips16): New patterns.
+	* config/mips/mips.c (mips_const_insns, mips_output_move): Remove
+	mips16 CONSTANT_RELOC handling.
+	(mips_delegitimize_address): Adjust for new sdata representation.
+
+2003-10-06  Richard Sandiford  <rsandifo@redhat.com>
+
 	* config/mips/mips.c (mips_arg_info): If MUST_PASS_IN_STACK,
 	skip any remaining register arguments.
 
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index bcd9586c955..304cf1dc86f 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -1202,6 +1202,8 @@ mips_address_insns (rtx x, enum machine_mode mode)
       return factor;
 
     case ADDRESS_LO_SUM:
+      return (TARGET_MIPS16 ? factor * 2 : factor);
+
     case ADDRESS_CONST_INT:
       return factor;
 
@@ -1250,12 +1252,8 @@ mips_const_insns (rtx x)
 	  return 0;
 
 	case CONSTANT_GP:
-	  return 1;
-
 	case CONSTANT_RELOC:
-	  /* When generating mips16 code, we need to set the destination to
-	     $0 and then add in the signed offset.  See mips_output_move.  */
-	  return (TARGET_MIPS16 ? 3 : 1);
+	  return 1;
 
 	case CONSTANT_SYMBOLIC:
 	  return mips_symbol_insns (mips_classify_symbol (c.symbol));
@@ -2013,12 +2011,11 @@ mips_delegitimize_address (rtx x)
       && mips_classify_symbol (c.symbol) == SYMBOL_GOT_GLOBAL)
     return c.symbol;
 
-  if (GET_CODE (x) == PLUS
-      && (XEXP (x, 0) == pic_offset_table_rtx
-	  || XEXP (x, 0) == cfun->machine->mips16_gp_pseudo_rtx)
-      && mips_classify_constant (&c, XEXP (x, 1)) == CONSTANT_RELOC
-      && mips_classify_symbol (c.symbol) == SYMBOL_SMALL_DATA)
-    return plus_constant (c.symbol, c.offset);
+  if (GET_CODE (x) == LO_SUM
+      && XEXP (x, 0) == (TARGET_MIPS16
+			 ? cfun->machine->mips16_gp_pseudo_rtx
+			 : pic_offset_table_rtx))
+    return XEXP (x, 1);
 
   return x;
 }
@@ -2721,7 +2718,7 @@ mips_output_move (rtx dest, rtx src)
 	  return "move\t%0,%1";
 
 	case CONSTANT_RELOC:
-	  return (TARGET_MIPS16 ? "li\t%0,0\n\taddiu\t%0,%1" : "li\t%0,%1");
+	  return "li\t%0,%1";
 
 	case CONSTANT_SYMBOLIC:
 	  return (dbl_p ? "dla\t%0,%a1" : "la\t%0,%a1");
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 18664397084..c6227ebe364 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4182,7 +4182,7 @@ dsrl\t%3,%3,1\n\
 ;; Operand 2 is the address: print_operand works out which relocation
 ;; should be applied.
 
-(define_insn "lowsi"
+(define_insn "*lowsi"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
 		   (match_operand:SI 2 "immediate_operand" "")))]
@@ -4191,7 +4191,7 @@ dsrl\t%3,%3,1\n\
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
-(define_insn "lowdi"
+(define_insn "*lowdi"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
 		   (match_operand:DI 2 "immediate_operand" "")))]
@@ -4200,6 +4200,26 @@ dsrl\t%3,%3,1\n\
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
+(define_insn "*lowsi_mips16"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(lo_sum:SI (match_operand:SI 1 "register_operand" "0")
+		   (match_operand:SI 2 "immediate_operand" "")))]
+  "TARGET_MIPS16"
+  "addiu\t%0,%R2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"8")])
+
+(define_insn "*lowdi_mips16"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(lo_sum:DI (match_operand:DI 1 "register_operand" "0")
+		   (match_operand:DI 2 "immediate_operand" "")))]
+  "TARGET_MIPS16 && TARGET_64BIT"
+  "daddiu\t%0,%R2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"8")])
+
 ;; 64-bit integer moves
 
 ;; Unlike most other insns, the move insns can't be split with