diff options
| author | kazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-02-23 14:17:25 +0000 |
|---|---|---|
| committer | kazu <kazu@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-02-23 14:17:25 +0000 |
| commit | 7ef78393e37611ce44704e0bf23fa6c0f33f9b8b (patch) | |
| tree | d28103d65d23658491754132417c209507f21759 /gcc | |
| parent | 4a1ea6f4bfb55aed43f78600932ae7aad48419e6 (diff) | |
| download | gcc-7ef78393e37611ce44704e0bf23fa6c0f33f9b8b.tar.gz | |
* config/h8300/h8300.c (output_simode_bld): Handle H8/300 and
H8/300[HS] separately.
* config/h8300/h8300.md: Remove the early clobber constraint
from bit field patterns.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@49995 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/h8300/h8300.c | 33 | ||||
| -rw-r--r-- | gcc/config/h8300/h8300.md | 4 |
3 files changed, 32 insertions, 12 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bc546ad344e..627202d5ccc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2002-02-23 Kazu Hirata <kazu@hxi.com> + * config/h8300/h8300.c (output_simode_bld): Handle H8/300 and + H8/300[HS] separately. + * config/h8300/h8300.md: Remove the early clobber constraint + from bit field patterns. + +2002-02-23 Kazu Hirata <kazu@hxi.com> + * config/h8300/h8300.md (mulqihi3): Tighten predicates to register_operand. (mulhisi3): Likewise. diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c index 629539d2446..63d5ee2530f 100644 --- a/gcc/config/h8300/h8300.c +++ b/gcc/config/h8300/h8300.c @@ -3120,18 +3120,31 @@ output_simode_bld (bild, operands) int bild; rtx operands[]; { - /* Clear the destination register. */ - if (TARGET_H8300H || TARGET_H8300S) - output_asm_insn ("sub.l\t%S0,%S0", operands); - else - output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands); + if (TARGET_H8300) + { + /* Clear the destination register. */ + output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands); + + /* Now output the bit load or bit inverse load, and store it in + the destination. */ + if (bild) + output_asm_insn ("bild\t%Z2,%Y1", operands); + else + output_asm_insn ("bld\t%Z2,%Y1", operands); - /* Now output the bit load or bit inverse load, and store it in - the destination. */ - if (bild) - output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands); + output_asm_insn ("bst\t#0,%w0", operands); + } else - output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands); + { + /* Output the bit load or bit inverse load. */ + if (bild) + output_asm_insn ("bild\t%Z2,%Y1", operands); + else + output_asm_insn ("bld\t%Z2,%Y1", operands); + + /* Clear the destination register and perform the bit store. */ + output_asm_insn ("xor.l\t%S0,%S0\n\tbst\t#0,%w0", operands); + } /* All done. */ return ""; diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index d99103efa60..51541af4330 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -2031,7 +2031,7 @@ (set_attr "length" "6")]) (define_insn "" - [(set (match_operand:SI 0 "register_operand" "=&r") + [(set (match_operand:SI 0 "register_operand" "=r") (zero_extract:SI (match_operand:SI 1 "register_operand" "r") (const_int 1) (match_operand 2 "const_int_operand" "n")))] @@ -2059,7 +2059,7 @@ (set_attr "length" "6")]) (define_insn "" - [(set (match_operand:SI 0 "register_operand" "=&r") + [(set (match_operand:SI 0 "register_operand" "=r") (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r") (match_operand 3 "const_int_operand" "n")) (const_int 1) |