always define SHORT_IMMEDIATES_SIGN_EXTEND

gcc/ChangeLog:

2015-07-08  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>

	* combine.c (update_rsp_from_reg_equal): Don't check if
	SHORT_IMMEDIATES_SIGN_EXTEND is defined.
	(reg_nonzero_bits_for_combine): Likewise.
	* config/alpha/alpha.h: Define SHORT_IMMEDIATES_SIGN_EXTEND to
	1.
	* config/frv/frv.h: Likewise.
	* config/lm32/lm32.h: Likewise.
	* config/mep/mep.h: Likewise.
	* config/mips/mips.h: Likewise.
	* config/rs6000/rs6000.h: Likewise.
	* config/sh/sh.h: Likewise.
	* config/tilegx/tilegx.h (enum reg_class): Likewise.
	* config/tilepro/tilepro.h: Likewise.
	* defaults.h: Add default for SHORT_IMMEDIATES_SIGN_EXTEND.
	* doc/tm.texi: Regenerate.
	* doc/tm.texi.in: Adjust.
	* rtlanal.c (nonzero_bits1): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225593 138bc75d-0d04-0410-961f-82ee72b054a4

15 files changed, 46 insertions, 25 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 59afe38ffef..2275e3b6b79 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,25 @@
 2015-07-08  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
 
+	* combine.c (update_rsp_from_reg_equal): Don't check if
+	SHORT_IMMEDIATES_SIGN_EXTEND is defined.
+	(reg_nonzero_bits_for_combine): Likewise.
+	* config/alpha/alpha.h: Define SHORT_IMMEDIATES_SIGN_EXTEND to
+	1.
+	* config/frv/frv.h: Likewise.
+	* config/lm32/lm32.h: Likewise.
+	* config/mep/mep.h: Likewise.
+	* config/mips/mips.h: Likewise.
+	* config/rs6000/rs6000.h: Likewise.
+	* config/sh/sh.h: Likewise.
+	* config/tilegx/tilegx.h (enum reg_class): Likewise.
+	* config/tilepro/tilepro.h: Likewise.
+	* defaults.h: Add default for SHORT_IMMEDIATES_SIGN_EXTEND.
+	* doc/tm.texi: Regenerate.
+	* doc/tm.texi.in: Adjust.
+	* rtlanal.c (nonzero_bits1): Likewise.
+
+2015-07-08  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
 	* combine.c (do_SUBST_MODE): Don't check the value of HAVE_cc0
 	with the preprocessor.
 	(combine_instructions): Likewise.
diff --git a/gcc/combine.c b/gcc/combine.c
index 19aa0e1e6b5..14d1468699a 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -1624,7 +1624,6 @@ setup_incoming_promotions (rtx_insn *first)
     }
 }
 
-#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
    that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
    because some machines (maybe most) will actually do the sign-extension and
@@ -1644,7 +1643,6 @@ sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
 
   return src;
 }
-#endif
 
 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
    and SET.  */
@@ -1661,11 +1659,12 @@ update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
   if (reg_equal_note)
     reg_equal = XEXP (reg_equal_note, 0);
 
-#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
-  src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
-  if (reg_equal)
-    reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
-#endif
+  if (SHORT_IMMEDIATES_SIGN_EXTEND)
+    {
+      src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
+      if (reg_equal)
+	reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
+    }
 
   /* Don't call nonzero_bits if it cannot change anything.  */
   if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
@@ -9824,10 +9823,10 @@ reg_nonzero_bits_for_combine (const_rtx x, machine_mode mode,
 
   if (tem)
     {
-#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
-      tem = sign_extend_short_imm (tem, GET_MODE (x),
-				   GET_MODE_PRECISION (mode));
-#endif
+      if (SHORT_IMMEDIATES_SIGN_EXTEND)
+	tem = sign_extend_short_imm (tem, GET_MODE (x),
+				     GET_MODE_PRECISION (mode));
+
       return tem;
     }
   else if (nonzero_sign_valid && rsp->nonzero_bits)
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index 8d2ab238157..c39f1031b0a 100644
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -897,7 +897,7 @@ do {									     \
 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 
 /* Define if loading short immediate values into registers sign extends.  */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
 
 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
    is done just by pretending it is already truncated.  */
diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h
index 2d4cbddeb74..a96f201b357 100644
--- a/gcc/config/frv/frv.h
+++ b/gcc/config/frv/frv.h
@@ -1899,7 +1899,7 @@ fprintf (STREAM, "\t.word .L%d\n", VALUE)
 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
 
 /* Define if loading short immediate values into registers sign extends.  */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
 
 /* The maximum number of bytes that a single instruction can move quickly from
    memory to memory.  */
diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h
index d2847035237..9872860ec62 100644
--- a/gcc/config/lm32/lm32.h
+++ b/gcc/config/lm32/lm32.h
@@ -525,7 +525,7 @@ do {                                                            \
 
 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
 
 #define MOVE_MAX        UNITS_PER_WORD
 #define MAX_MOVE_MAX    4
diff --git a/gcc/config/mep/mep.h b/gcc/config/mep/mep.h
index 861189d5420..8fee2735a63 100644
--- a/gcc/config/mep/mep.h
+++ b/gcc/config/mep/mep.h
@@ -765,7 +765,7 @@ typedef struct
 #define WORD_REGISTER_OPERATIONS
 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
 
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
 
 #define MOVE_MAX 4
 
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 7a6f9171ac7..03bbae1ad5a 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1626,7 +1626,7 @@ FP_ASM_SPEC "\
 #define POINTERS_EXTEND_UNSIGNED false
 
 /* Define if loading short immediate values into registers sign extends.  */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
 
 /* The [d]clz instructions have the natural values at 0.  */
 
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ef8ff38b96a..3bd2048b82c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2046,7 +2046,7 @@ do {									     \
 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 
 /* Define if loading short immediate values into registers sign extends.  */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
 
 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
    is done just by pretending it is already truncated.  */
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 3078880a69a..c4947a68179 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1827,7 +1827,7 @@ struct sh_args {
   : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
 
 /* Define if loading short immediate values into registers sign extends.  */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
 
 /* Nonzero if access to memory by bytes is no faster than for words.  */
 #define SLOW_BYTE_ACCESS 1
diff --git a/gcc/config/tilegx/tilegx.h b/gcc/config/tilegx/tilegx.h
index 5fa10b39e39..7c3995abecc 100644
--- a/gcc/config/tilegx/tilegx.h
+++ b/gcc/config/tilegx/tilegx.h
@@ -386,7 +386,7 @@ enum reg_class
 
 #define SHIFT_COUNT_TRUNCATED 0
 
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
 
 /* We represent all SI values as sign-extended DI values in
    registers.  */
diff --git a/gcc/config/tilepro/tilepro.h b/gcc/config/tilepro/tilepro.h
index f2b7b163270..970135a1d96 100644
--- a/gcc/config/tilepro/tilepro.h
+++ b/gcc/config/tilepro/tilepro.h
@@ -346,7 +346,7 @@ enum reg_class
 
 #define SHIFT_COUNT_TRUNCATED 1
 
-#define SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
 
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 
diff --git a/gcc/defaults.h b/gcc/defaults.h
index 5beddea669e..f0296a3e472 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -1265,6 +1265,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_SUPPORTS_WIDE_INT 0
 #endif
 
+#ifndef SHORT_IMMEDIATES_SIGN_EXTEND
+#define SHORT_IMMEDIATES_SIGN_EXTEND 0
+#endif
+
 #ifdef GCC_INSN_FLAGS_H
 /* Dependent default target macro definitions
 
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 3dc51c00b9a..a67b6a1c4f3 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -10410,7 +10410,7 @@ is larger then @var{mem_mode} but still smaller than @code{word_mode}.
 @end defmac
 
 @defmac SHORT_IMMEDIATES_SIGN_EXTEND
-Define this macro if loading short immediate values into registers sign
+Define this macro to 1 if loading short immediate values into registers sign
 extends.
 @end defmac
 
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 93fb41c6879..59aa589bec9 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -7534,7 +7534,7 @@ is larger then @var{mem_mode} but still smaller than @code{word_mode}.
 @end defmac
 
 @defmac SHORT_IMMEDIATES_SIGN_EXTEND
-Define this macro if loading short immediate values into registers sign
+Define this macro to 1 if loading short immediate values into registers sign
 extends.
 @end defmac
 
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 854d74183de..e910ae7985f 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -4327,14 +4327,12 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
       }
 
     case CONST_INT:
-#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
       /* If X is negative in MODE, sign-extend the value.  */
-      if (INTVAL (x) > 0
+      if (SHORT_IMMEDIATES_SIGN_EXTEND && INTVAL (x) > 0
 	  && mode_width < BITS_PER_WORD
 	  && (UINTVAL (x) & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
 	     != 0)
 	return UINTVAL (x) | (HOST_WIDE_INT_M1U << mode_width);
-#endif
 
       return UINTVAL (x);