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authoralalaw01 <alalaw01@138bc75d-0d04-0410-961f-82ee72b054a4>2015-06-24 16:26:38 +0000
committeralalaw01 <alalaw01@138bc75d-0d04-0410-961f-82ee72b054a4>2015-06-24 16:26:38 +0000
commit14a6e10c3985adc02f126b1ce5a2f52906e52349 (patch)
tree4a670dc7c46d8dd96bed2bd2c30914585ac4ca70 /gcc
parent33cb48f09f1eef3eca649caf463017ee0833f3e5 (diff)
downloadgcc-14a6e10c3985adc02f126b1ce5a2f52906e52349.tar.gz
[AArch64] Fix another ICE with -mgeneral-regs-only
gcc/: * config/aarch64/aarch64.md (<optab><fcvt_target><GPF:mode>2): Condition on TARGET_FLOAT. gcc/testsuite/: * gcc.target/aarch64/mgeneral-regs_3.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@224910 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/aarch64/aarch64.md2
-rw-r--r--gcc/testsuite/ChangeLog4
-rw-r--r--gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c11
4 files changed, 21 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bf4f27c3d51..944e89c5fa5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
2015-06-24 Alan Lawrence <alan.lawrence@arm.com>
+ * config/aarch64/aarch64.md (<optab><fcvt_target><GPF:mode>2):
+ Condition on TARGET_FLOAT.
+
+2015-06-24 Alan Lawrence <alan.lawrence@arm.com>
+
* doc/invoke.texi: Clarify AArch64 feature modifiers (no)fp, (no)simd
and (no)crypto.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 934c8faf6d6..dbc4d1fbfee 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4117,7 +4117,7 @@
(define_insn "<optab><fcvt_target><GPF:mode>2"
[(set (match_operand:GPF 0 "register_operand" "=w,w")
(FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,r")))]
- ""
+ "TARGET_FLOAT"
"@
<su_optab>cvtf\t%<GPF:s>0, %<s>1
<su_optab>cvtf\t%<GPF:s>0, %<w1>1"
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b9084a6e393..61045d38d2a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,9 @@
2015-06-24 Alan Lawrence <alan.lawrence@arm.com>
+ * gcc.target/aarch64/mgeneral-regs_3.c: New.
+
+2015-06-24 Alan Lawrence <alan.lawrence@arm.com>
+
* gcc.target/aarch64/mgeneral-regs_1.c: New file.
* gcc.target/aarch64/mgeneral-regs_2.c: New file.
* gcc.target/aarch64/nofp_1.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c
new file mode 100644
index 00000000000..f6b5fbae70b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c
@@ -0,0 +1,11 @@
+/* { dg-options "-mgeneral-regs-only -O2" } */
+
+extern void abort (void);
+
+int
+test (int i, ...)
+{
+ float f = (float) i; /* { dg-error "'-mgeneral-regs-only' is incompatible with floating-point code" } */
+ if (f != f) abort ();
+ return 2;
+}