diff options
| author | cltang <cltang@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-01-26 03:01:44 +0000 |
|---|---|---|
| committer | cltang <cltang@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-01-26 03:01:44 +0000 |
| commit | 06a9ac974c8f44b968450f68c52a3f124b097b53 (patch) | |
| tree | f2095a0bd1a83bd7813461fad725197e20e9faf6 /gcc | |
| parent | 509475fdaae4bb08637c9603a303f0fe2cd9a277 (diff) | |
| download | gcc-06a9ac974c8f44b968450f68c52a3f124b097b53.tar.gz | |
2011-01-26 Chung-Lin Tang <cltang@codesourcery.com>
PR target/47246
* config/arm/arm.c (thumb2_legitimate_index_p): Change the
lower bound of the allowed Thumb-2 coprocessor load/store
index range to -256. Add explaining comment.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@169271 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 6 |
2 files changed, 12 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c26fb8f1e7b..0997ccea8ac 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2011-01-26 Chung-Lin Tang <cltang@codesourcery.com> + + PR target/47246 + * config/arm/arm.c (thumb2_legitimate_index_p): Change the + lower bound of the allowed Thumb-2 coprocessor load/store + index range to -256. Add explaining comment. + 2011-01-25 Ian Lance Taylor <iant@google.com> * godump.c (go_define): Improve lexing of macro expansion to only diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index be09282c17d..b93756a8ef4 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -5786,7 +5786,11 @@ thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) && (mode == SFmode || mode == DFmode || (TARGET_MAVERICK && mode == DImode))) return (code == CONST_INT && INTVAL (index) < 1024 - && INTVAL (index) > -1024 + /* Thumb-2 allows only > -256 index range for it's core register + load/stores. Since we allow SF/DF in core registers, we have + to use the intersection between -256~4096 (core) and -1024~1024 + (coprocessor). */ + && INTVAL (index) > -256 && (INTVAL (index) & 3) == 0); if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) |