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| author | Alexandre Oliva <aoliva@redhat.com> | 2002-03-16 23:53:09 +0000 |
|---|---|---|
| committer | Alexandre Oliva <aoliva@gcc.gnu.org> | 2002-03-16 23:53:09 +0000 |
| commit | 4f5bd6d713dc20d5b57a1619ad578284f20d4b89 (patch) | |
| tree | efae5fffd56a4fc291a317f31afb95df8b512785 /gcc | |
| parent | c8d1b2b7b2864a1383fd22d3bf71e1fe80347c6c (diff) | |
| download | gcc-4f5bd6d713dc20d5b57a1619ad578284f20d4b89.tar.gz | |
mips.md (addsi3, adddi3): Use scratch register to add register to non-constant into sp.
* config/mips/mips.md (addsi3, adddi3): Use scratch register to
add register to non-constant into sp.
From-SVN: r50897
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 3 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 42 |
2 files changed, 45 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0216c1b3096..4ff4a5c994f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,8 @@ 2002-03-16 Alexandre Oliva <aoliva@redhat.com> + * config/mips/mips.md (addsi3, adddi3): Use scratch register to + add register to non-constant into sp. + * config/mips/mips-protos.h (embedded_pic_fnaddr_reg): New. * config/mips/mips.h (embedded_pic_fnaddr_rtx): Lose. (mips16_gp_pseudo_rtx): Lose. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 536443bf087..91df86cc052 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -614,6 +614,27 @@ && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768) operands[2] = force_reg (SImode, operands[2]); + + /* If a large stack adjustment was forced into a register, we may be + asked to generate rtx such as: + + (set (reg:SI sp) (plus:SI (reg:SI sp) (reg:SI pseudo))) + + but no such instruction is available in mips16. Handle it by + using a temporary. */ + if (TARGET_MIPS16 + && REGNO (operands[0]) == STACK_POINTER_REGNUM + && ((GET_CODE (operands[1]) == REG + && REGNO (operands[1]) != STACK_POINTER_REGNUM) + || GET_CODE (operands[2]) != CONST_INT)) + { + rtx tmp = gen_reg_rtx (SImode); + + emit_move_insn (tmp, operands[1]); + emit_insn (gen_addsi3 (tmp, tmp, operands[2])); + emit_move_insn (operands[0], tmp); + DONE; + } }") (define_insn "addsi3_internal" @@ -777,6 +798,27 @@ && INTVAL (operands[2]) == -32768) operands[2] = force_reg (DImode, operands[2]); + /* If a large stack adjustment was forced into a register, we may be + asked to generate rtx such as: + + (set (reg:DI sp) (plus:DI (reg:DI sp) (reg:DI pseudo))) + + but no such instruction is available in mips16. Handle it by + using a temporary. */ + if (TARGET_MIPS16 + && REGNO (operands[0]) == STACK_POINTER_REGNUM + && ((GET_CODE (operands[1]) == REG + && REGNO (operands[1]) != STACK_POINTER_REGNUM) + || GET_CODE (operands[2]) != CONST_INT)) + { + rtx tmp = gen_reg_rtx (DImode); + + emit_move_insn (tmp, operands[1]); + emit_insn (gen_addsi3 (tmp, tmp, operands[2])); + emit_move_insn (operands[0], tmp); + DONE; + } + if (TARGET_64BIT) { emit_insn (gen_adddi3_internal_3 (operands[0], operands[1], |