always define WORD_REGISTER_OPERATIONS

gcc/ChangeLog:

2015-07-08  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>

	* defaults.h: Provide default for WORD_REGISTER_OPERATIONS.
	* config/alpha/alpha.h: Define WORD_REGISTER_OPERATIONS to 1.
	* config/arc/arc.h: Likewise.
	* config/arm/arm.h: Likewise.
	* config/bfin/bfin.h: Likewise.
	* config/epiphany/epiphany.h: Likewise.
	* config/frv/frv.h: Likewise.
	* config/ia64/ia64.h: Likewise.
	* config/iq2000/iq2000.h: Likewise.
	* config/lm32/lm32.h: Likewise.
	* config/m32r/m32r.h: Likewise.
	* config/mcore/mcore.h: Likewise.
	* config/mep/mep.h: Likewise.
	* config/microblaze/microblaze.h: Likewise.
	* config/mips/mips.h: Likewise.
	* config/mmix/mmix.h: Likewise.
	* config/mn10300/mn10300.h: Likewise.
	* config/nds32/nds32.h: Likewise.
	* config/nios2/nios2.h: Likewise.
	* config/pa/pa.h: Likewise.
	* config/rl78/rl78.h: Likewise.
	* config/sh/sh.h: Likewise.
	* config/sparc/sparc.h: Likewise.
	* config/stormy16/stormy16.h: Likewise.
	* config/tilegx/tilegx.h: Likewise.
	* config/tilepro/tilepro.h: Likewise.
	* config/v850/v850.h: Likewise.
	* config/xtensa/xtensa.h: Likewise.
	* doc/tm.texi: Regenerate.
	* doc/tm.texi.in: Adjust.
	* combine.c (simplify_set): Likewise.
	(simplify_comparison): Likewise.
	* expr.c (store_constructor): Likewise.
	* internal-fn.c (expand_arith_overflow): Likewise.
	* reload.c (push_reload): Likewise.
	(find_reloads): Likewise.
	(find_reloads_subreg_address): Likewise.
	* reload1.c (eliminate_regs_1): Likewise.
	* rtlanal.c (nonzero_bits1): Likewise.
	(num_sign_bit_copies1): Likewise.
	* simplify-rtx.c (simplify_truncation): Likewise.

From-SVN: r225597

38 files changed, 113 insertions, 77 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6ddd1ce78ce..c54e138220c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,49 @@
 2015-07-08  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
 
+	* defaults.h: Provide default for WORD_REGISTER_OPERATIONS.
+	* config/alpha/alpha.h: Define WORD_REGISTER_OPERATIONS to 1.
+	* config/arc/arc.h: Likewise.
+	* config/arm/arm.h: Likewise.
+	* config/bfin/bfin.h: Likewise.
+	* config/epiphany/epiphany.h: Likewise.
+	* config/frv/frv.h: Likewise.
+	* config/ia64/ia64.h: Likewise.
+	* config/iq2000/iq2000.h: Likewise.
+	* config/lm32/lm32.h: Likewise.
+	* config/m32r/m32r.h: Likewise.
+	* config/mcore/mcore.h: Likewise.
+	* config/mep/mep.h: Likewise.
+	* config/microblaze/microblaze.h: Likewise.
+	* config/mips/mips.h: Likewise.
+	* config/mmix/mmix.h: Likewise.
+	* config/mn10300/mn10300.h: Likewise.
+	* config/nds32/nds32.h: Likewise.
+	* config/nios2/nios2.h: Likewise.
+	* config/pa/pa.h: Likewise.
+	* config/rl78/rl78.h: Likewise.
+	* config/sh/sh.h: Likewise.
+	* config/sparc/sparc.h: Likewise.
+	* config/stormy16/stormy16.h: Likewise.
+	* config/tilegx/tilegx.h: Likewise.
+	* config/tilepro/tilepro.h: Likewise.
+	* config/v850/v850.h: Likewise.
+	* config/xtensa/xtensa.h: Likewise.
+	* doc/tm.texi: Regenerate.
+	* doc/tm.texi.in: Adjust.
+	* combine.c (simplify_set): Likewise.
+	(simplify_comparison): Likewise.
+	* expr.c (store_constructor): Likewise.
+	* internal-fn.c (expand_arith_overflow): Likewise.
+	* reload.c (push_reload): Likewise.
+	(find_reloads): Likewise.
+	(find_reloads_subreg_address): Likewise.
+	* reload1.c (eliminate_regs_1): Likewise.
+	* rtlanal.c (nonzero_bits1): Likewise.
+	(num_sign_bit_copies1): Likewise.
+	* simplify-rtx.c (simplify_truncation): Likewise.
+
+2015-07-08  Trevor Saunders  <tbsaunde+gcc@tbsaunde.org>
+
 	* auto-inc-dec.c (pass_inc_dec::execute): Don't check the value
 	of AUTO_INC_DEC with the preprocessor.
 	* combine.c (combine_instructions): Likewise.
diff --git a/gcc/combine.c b/gcc/combine.c
index d68515c2898..e4e1d3ab656 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -6716,10 +6716,9 @@ simplify_set (rtx x)
 	   / UNITS_PER_WORD)
 	  == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
 	       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
-#ifndef WORD_REGISTER_OPERATIONS
-      && (GET_MODE_SIZE (GET_MODE (src))
-	< GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
-#endif
+      && (WORD_REGISTER_OPERATIONS
+	  || (GET_MODE_SIZE (GET_MODE (src))
+	      < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
 #ifdef CANNOT_CHANGE_MODE_CLASS
       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
 	    && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
@@ -11424,7 +11423,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
   /* Try a few ways of applying the same transformation to both operands.  */
   while (1)
     {
-#ifndef WORD_REGISTER_OPERATIONS
+#if !WORD_REGISTER_OPERATIONS
       /* The test below this one won't handle SIGN_EXTENDs on these machines,
 	 so check specially.  */
       if (code != GTU && code != GEU && code != LTU && code != LEU
@@ -12078,11 +12077,9 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
 		     However, if we commute the AND inside the SUBREG then
 		     they no longer have defined values and the meaning of
 		     the code has been changed.  */
-		  && (0
-#ifdef WORD_REGISTER_OPERATIONS
-		      || (mode_width > GET_MODE_PRECISION (tmode)
-			  && mode_width <= BITS_PER_WORD)
-#endif
+		  && ((WORD_REGISTER_OPERATIONS
+		       && mode_width > GET_MODE_PRECISION (tmode)
+		       && mode_width <= BITS_PER_WORD)
 		      || (mode_width <= GET_MODE_PRECISION (tmode)
 			  && subreg_lowpart_p (XEXP (op0, 0))))
 		  && CONST_INT_P (XEXP (op0, 1))
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index c39f1031b0a..3fb58b11b0d 100644
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -888,7 +888,7 @@ do {									     \
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
    will either zero-extend or sign-extend.  The value of this macro should
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 4fdd6543415..d98cce11257 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -1540,7 +1540,7 @@ extern int arc_return_address_regs[4];
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
    will either zero-extend or sign-extend.  The value of this macro should
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 373dc85778d..836e5179d9b 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1904,7 +1904,7 @@ enum arm_auto_incmodes
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
    will either zero-extend or sign-extend.  The value of this macro should
diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h
index b0d017ebf5c..26ba7c2e015 100644
--- a/gcc/config/bfin/bfin.h
+++ b/gcc/config/bfin/bfin.h
@@ -982,7 +982,7 @@ typedef struct {
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified. 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 */
 
 /* Evaluates to true if A and B are mac flags that can be used
diff --git a/gcc/config/epiphany/epiphany.h b/gcc/config/epiphany/epiphany.h
index 5515edbe9f0..62a3d9d7ee6 100644
--- a/gcc/config/epiphany/epiphany.h
+++ b/gcc/config/epiphany/epiphany.h
@@ -845,7 +845,7 @@ do \
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
    will either zero-extend or sign-extend.  The value of this macro should
diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h
index a96f201b357..b0d66fdf610 100644
--- a/gcc/config/frv/frv.h
+++ b/gcc/config/frv/frv.h
@@ -1882,7 +1882,7 @@ fprintf (STREAM, "\t.word .L%d\n", VALUE)
 /* Define this macro if operations between registers with integral mode smaller
    than a word are always performed on the entire register.  Most RISC machines
    have this property and most CISC machines do not.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define this macro to be a C expression indicating when insns that read
    memory in MODE, an integral mode narrower than a word, set the bits outside
diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h
index 943faf9e0a9..4b624237a48 100644
--- a/gcc/config/ia64/ia64.h
+++ b/gcc/config/ia64/ia64.h
@@ -1631,7 +1631,7 @@ do {									\
 /* Define this macro if operations between registers with integral mode smaller
    than a word are always performed on the entire register.  */
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define this macro to be a C expression indicating when insns that read
    memory in MODE, an integral mode narrower than a word, set the bits outside
diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h
index 14a68ce40a5..73b1205db1c 100644
--- a/gcc/config/iq2000/iq2000.h
+++ b/gcc/config/iq2000/iq2000.h
@@ -541,7 +541,7 @@ while (0)
 
 #define CASE_VECTOR_MODE SImode
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 
diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h
index 9872860ec62..986383f91b0 100644
--- a/gcc/config/lm32/lm32.h
+++ b/gcc/config/lm32/lm32.h
@@ -521,7 +521,7 @@ do {                                                            \
 
 #define CASE_VECTOR_MODE Pmode
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h
index 2163de41349..fa061351f38 100644
--- a/gcc/config/m32r/m32r.h
+++ b/gcc/config/m32r/m32r.h
@@ -1004,7 +1004,7 @@ L2:     .word STATIC
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
    will either zero-extend or sign-extend.  The value of this macro should
diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h
index 0aa96807b71..999d53603e1 100644
--- a/gcc/config/mcore/mcore.h
+++ b/gcc/config/mcore/mcore.h
@@ -639,7 +639,7 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
    will either zero-extend or sign-extend.  The value of this macro should
@@ -673,7 +673,7 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
    and another.  All register moves are cheap.  */
 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Assembler output control.  */
 #define ASM_COMMENT_START "\t//"
diff --git a/gcc/config/mep/mep.h b/gcc/config/mep/mep.h
index 8fee2735a63..f7322cb7c56 100644
--- a/gcc/config/mep/mep.h
+++ b/gcc/config/mep/mep.h
@@ -762,7 +762,7 @@ typedef struct
 
 #define CASE_VECTOR_MODE SImode
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
 
 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
index c832fa0fe93..482c4a25d20 100644
--- a/gcc/config/microblaze/microblaze.h
+++ b/gcc/config/microblaze/microblaze.h
@@ -235,7 +235,7 @@ extern enum pipeline_type microblaze_pipe;
        && TYPE_MODE (TREE_TYPE (TYPE)) == QImode)			\
      && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
 
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 03bbae1ad5a..37c85f0f055 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1598,7 +1598,7 @@ FP_ASM_SPEC "\
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
    moves.  All other references are zero extended.  */
diff --git a/gcc/config/mmix/mmix.h b/gcc/config/mmix/mmix.h
index 61ae4d694eb..d15d90e54a3 100644
--- a/gcc/config/mmix/mmix.h
+++ b/gcc/config/mmix/mmix.h
@@ -793,7 +793,7 @@ typedef struct { int regs; int lib; } CUMULATIVE_ARGS;
 #define CASE_VECTOR_MODE DImode
 #define CASE_VECTOR_PC_RELATIVE 0
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* We have a choice, which makes this yet another parameter to tweak.  The
    gut feeling is currently that SIGN_EXTEND wins; "int" is more frequent
diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h
index e5fa70bd7a8..dbedb18e40c 100644
--- a/gcc/config/mn10300/mn10300.h
+++ b/gcc/config/mn10300/mn10300.h
@@ -699,7 +699,7 @@ do {									     \
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 
diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h
index dcecea72208..126b5861d80 100644
--- a/gcc/config/nds32/nds32.h
+++ b/gcc/config/nds32/nds32.h
@@ -1001,7 +1001,7 @@ enum reg_class
 
 /* Define this macro if operations between registers with integral mode
    smaller than a word are always performed on the entire register.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* A C expression indicating when insns that read memory in mem_mode,
    an integral mode narrower than a word, set the bits outside of mem_mode
diff --git a/gcc/config/nios2/nios2.h b/gcc/config/nios2/nios2.h
index 45eb70b7cec..5856d7dccf6 100644
--- a/gcc/config/nios2/nios2.h
+++ b/gcc/config/nios2/nios2.h
@@ -497,6 +497,6 @@ do {                                                                    \
 
 #define LOAD_EXTEND_OP(MODE) (ZERO_EXTEND)
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 #endif /* GCC_NIOS2_H */
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 4259a07d1eb..d7daabf081d 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -1011,7 +1011,7 @@ do {									     \
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
    will either zero-extend or sign-extend.  The value of this macro should
diff --git a/gcc/config/rl78/rl78.h b/gcc/config/rl78/rl78.h
index 066b0d1323c..6c72fac938b 100644
--- a/gcc/config/rl78/rl78.h
+++ b/gcc/config/rl78/rl78.h
@@ -144,7 +144,7 @@
 #define POINTERS_EXTEND_UNSIGNED	1
 #define FUNCTION_MODE 			HImode
 #define CASE_VECTOR_MODE		Pmode
-#define WORD_REGISTER_OPERATIONS	0
+#define WORD_REGISTER_OPERATIONS	1
 #define HAS_LONG_COND_BRANCH		0
 #define HAS_LONG_UNCOND_BRANCH		0
 
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index c4947a68179..7aa489d6dc0 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1813,7 +1813,7 @@ struct sh_args {
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
    will either zero-extend or sign-extend.  The value of this macro should
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 72dd18bfdfc..2cbe0d9b7fa 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1460,7 +1460,7 @@ do {									   \
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
    will either zero-extend or sign-extend.  The value of this macro should
diff --git a/gcc/config/stormy16/stormy16.h b/gcc/config/stormy16/stormy16.h
index 38a2a0676a6..ef787fdd3fe 100644
--- a/gcc/config/stormy16/stormy16.h
+++ b/gcc/config/stormy16/stormy16.h
@@ -487,7 +487,7 @@ enum reg_class
 
 #define CASE_VECTOR_MODE SImode
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 
diff --git a/gcc/config/tilegx/tilegx.h b/gcc/config/tilegx/tilegx.h
index 7c3995abecc..ac134b9d64c 100644
--- a/gcc/config/tilegx/tilegx.h
+++ b/gcc/config/tilegx/tilegx.h
@@ -367,7 +367,7 @@ enum reg_class
 #define CLEAR_RATIO(speed) ((speed) ? 15 : TILEGX_CALL_RATIO)
 #define SET_RATIO(speed) ((speed) ? 15 : TILEGX_CALL_RATIO)
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 
diff --git a/gcc/config/tilepro/tilepro.h b/gcc/config/tilepro/tilepro.h
index 970135a1d96..a6d8c4eceb0 100644
--- a/gcc/config/tilepro/tilepro.h
+++ b/gcc/config/tilepro/tilepro.h
@@ -331,7 +331,7 @@ enum reg_class
 #define CLEAR_RATIO(speed) ((speed) ? 15 : TILEPRO_CALL_RATIO)
 #define SET_RATIO(speed) ((speed) ? 15 : TILEPRO_CALL_RATIO)
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 
diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h
index e40fd87789a..45ff1d596d1 100644
--- a/gcc/config/v850/v850.h
+++ b/gcc/config/v850/v850.h
@@ -864,7 +864,7 @@ typedef enum
 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
   ASM_OUTPUT_ALIGN ((FILE), (TARGET_BIG_SWITCH ? 2 : 1));
 
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Byte and short loads sign extend the value to a word.  */
 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index fb8702c92c9..ebc8792f90a 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -197,7 +197,7 @@ extern unsigned xtensa_current_frame_size;
 
 /* Operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
 
 /* Xtensa loads are zero-extended by default.  */
 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
diff --git a/gcc/defaults.h b/gcc/defaults.h
index f0296a3e472..9d38ba18ff4 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -1269,6 +1269,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define SHORT_IMMEDIATES_SIGN_EXTEND 0
 #endif
 
+#ifndef WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 0
+#endif
+
 #ifdef GCC_INSN_FLAGS_H
 /* Dependent default target macro definitions
 
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index a67b6a1c4f3..b911b7d4e26 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -10377,7 +10377,7 @@ five otherwise.  This is best for most machines.
 @end deftypefn
 
 @defmac WORD_REGISTER_OPERATIONS
-Define this macro if operations between registers with integral mode
+Define this macro to 1 if operations between registers with integral mode
 smaller than a word are always performed on the entire register.
 Most RISC machines have this property and most CISC machines do not.
 @end defmac
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 59aa589bec9..47550cc9861 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -7501,7 +7501,7 @@ is in effect.
 @hook TARGET_CASE_VALUES_THRESHOLD
 
 @defmac WORD_REGISTER_OPERATIONS
-Define this macro if operations between registers with integral mode
+Define this macro to 1 if operations between registers with integral mode
 smaller than a word are always performed on the entire register.
 Most RISC machines have this property and most CISC machines do not.
 @end defmac
diff --git a/gcc/expr.c b/gcc/expr.c
index 4b860ddf771..34930c506ed 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -5979,9 +5979,7 @@ static void
 store_constructor (tree exp, rtx target, int cleared, HOST_WIDE_INT size)
 {
   tree type = TREE_TYPE (exp);
-#ifdef WORD_REGISTER_OPERATIONS
   HOST_WIDE_INT exp_size = int_size_in_bytes (type);
-#endif
 
   switch (TREE_CODE (type))
     {
@@ -6094,13 +6092,13 @@ store_constructor (tree exp, rtx target, int cleared, HOST_WIDE_INT size)
 					 highest_pow2_factor (offset));
 	      }
 
-#ifdef WORD_REGISTER_OPERATIONS
 	    /* If this initializes a field that is smaller than a
 	       word, at the start of a word, try to widen it to a full
 	       word.  This special case allows us to output C++ member
 	       function initializations in a form that the optimizers
 	       can understand.  */
-	    if (REG_P (target)
+	    if (WORD_REGISTER_OPERATIONS
+		&& REG_P (target)
 		&& bitsize < BITS_PER_WORD
 		&& bitpos % BITS_PER_WORD == 0
 		&& GET_MODE_CLASS (mode) == MODE_INT
@@ -6125,7 +6123,6 @@ store_constructor (tree exp, rtx target, int cleared, HOST_WIDE_INT size)
 		bitsize = BITS_PER_WORD;
 		mode = word_mode;
 	      }
-#endif
 
 	    if (MEM_P (to_rtx) && !MEM_KEEP_ALIAS_SET_P (to_rtx)
 		&& DECL_NONADDRESSABLE_P (field))
diff --git a/gcc/internal-fn.c b/gcc/internal-fn.c
index 5b0a44d3d79..82d59c92ecf 100644
--- a/gcc/internal-fn.c
+++ b/gcc/internal-fn.c
@@ -1727,15 +1727,15 @@ expand_arith_overflow (enum tree_code code, gimple stmt)
 	  return;
 	}
 
-#ifdef WORD_REGISTER_OPERATIONS
       /* For sub-word operations, if target doesn't have them, start
 	 with precres widening right away, otherwise do it only
 	 if the most simple cases can't be used.  */
-      if (orig_precres == precres && precres < BITS_PER_WORD)
+      if (WORD_REGISTER_OPERATIONS
+	  && orig_precres == precres
+	  && precres < BITS_PER_WORD)
 	;
-      else
-#endif
-      if ((uns0_p && uns1_p && unsr_p && prec0 <= precres && prec1 <= precres)
+      else if ((uns0_p && uns1_p && unsr_p && prec0 <= precres
+		&& prec1 <= precres)
 	  || ((!uns0_p || !uns1_p) && !unsr_p
 	      && prec0 + uns0_p <= precres
 	      && prec1 + uns1_p <= precres))
@@ -1764,7 +1764,7 @@ expand_arith_overflow (enum tree_code code, gimple stmt)
       /* For sub-word operations, retry with a wider type first.  */
       if (orig_precres == precres && precop <= BITS_PER_WORD)
 	{
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
 	  int p = BITS_PER_WORD;
 #else
 	  int p = precop;
diff --git a/gcc/reload.c b/gcc/reload.c
index a670f13b72b..cc61d771efa 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -1086,7 +1086,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
 		      && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in)))
 		      && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN)
 #endif
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
 		  || ((GET_MODE_PRECISION (inmode)
 		       < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in))))
 		      && ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD ==
@@ -1124,8 +1124,9 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
 #endif
       inloc = &SUBREG_REG (in);
       in = *inloc;
-#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
-      if (MEM_P (in))
+#if ! defined (LOAD_EXTEND_OP)
+      if (!WORD_REGISTER_OPERATIONS
+	  && MEM_P (in))
 	/* This is supposed to happen only for paradoxical subregs made by
 	   combine.c.  (SUBREG (MEM)) isn't supposed to occur other ways.  */
 	gcc_assert (GET_MODE_SIZE (GET_MODE (in)) <= GET_MODE_SIZE (inmode));
@@ -1186,7 +1187,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
 	       || MEM_P (SUBREG_REG (out)))
 	      && ((GET_MODE_PRECISION (outmode)
 		   > GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out))))
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
 		  || ((GET_MODE_PRECISION (outmode)
 		       < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out))))
 		      && ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD ==
@@ -1220,11 +1221,9 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
 #endif
       outloc = &SUBREG_REG (out);
       out = *outloc;
-#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
-      gcc_assert (!MEM_P (out)
+      gcc_assert (WORD_REGISTER_OPERATIONS || !MEM_P (out)
 		  || GET_MODE_SIZE (GET_MODE (out))
 		     <= GET_MODE_SIZE (outmode));
-#endif
       outmode = GET_MODE (out);
     }
 
@@ -3152,7 +3151,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
 		      || ((MEM_P (operand)
 			   || (REG_P (operand)
 			       && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
-#ifndef WORD_REGISTER_OPERATIONS
+#if !WORD_REGISTER_OPERATIONS
 			  && (((GET_MODE_BITSIZE (GET_MODE (operand))
 				< BIGGEST_ALIGNMENT)
 			       && (GET_MODE_SIZE (operand_mode[i])
@@ -6160,12 +6159,11 @@ find_reloads_subreg_address (rtx x, int opnum, enum reload_type type,
   if (paradoxical_subreg_p (x))
     return NULL;
 
-#ifdef WORD_REGISTER_OPERATIONS
-  if (GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode)
+  if (WORD_REGISTER_OPERATIONS
+      && GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode)
       && ((GET_MODE_SIZE (outer_mode) - 1) / UNITS_PER_WORD
           == (GET_MODE_SIZE (inner_mode) - 1) / UNITS_PER_WORD))
     return NULL;
-#endif
 
   /* Since we don't attempt to handle paradoxical subregs, we can just
      call into simplify_subreg, which will handle all remaining checks
diff --git a/gcc/reload1.c b/gcc/reload1.c
index 956f0eb2a1b..5192a99a3ce 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -2862,7 +2862,7 @@ eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
 
 	  if (MEM_P (new_rtx)
 	      && ((x_size < new_size
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
 		   /* On these machines, combine can create rtl of the form
 		      (set (subreg:m1 (reg:m2 R) 0) ...)
 		      where m1 < m2, and expects something interesting to
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index e910ae7985f..cb20c2537dc 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -4253,7 +4253,6 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
        just return the mode mask.  Those tests will then be false.  */
     return nonzero;
 
-#ifndef WORD_REGISTER_OPERATIONS
   /* If MODE is wider than X, but both are a single word for both the host
      and target machines, we can compute this from which bits of the
      object might be nonzero in its own mode, taking into account the fact
@@ -4261,7 +4260,9 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
      causes the high-order bits to become undefined.  So they are
      not known to be zero.  */
 
-  if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
+  if (!WORD_REGISTER_OPERATIONS
+      && GET_MODE (x) != VOIDmode
+      && GET_MODE (x) != mode
       && GET_MODE_PRECISION (GET_MODE (x)) <= BITS_PER_WORD
       && GET_MODE_PRECISION (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
       && GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (GET_MODE (x)))
@@ -4271,7 +4272,6 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
       nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
       return nonzero;
     }
-#endif
 
   code = GET_CODE (x);
   switch (code)
@@ -4543,7 +4543,7 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
 	  nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
 					  known_x, known_mode, known_ret);
 
-#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
+#if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
 	  /* If this is a typical RISC machine, we only have to worry
 	     about the way loads are extended.  */
 	  if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
@@ -4763,12 +4763,12 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
 
   if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_PRECISION (GET_MODE (x)))
     {
-#ifndef WORD_REGISTER_OPERATIONS
       /* If this machine does not do all register operations on the entire
 	 register and MODE is wider than the mode of X, we can say nothing
 	 at all about the high-order bits.  */
-      return 1;
-#else
+      if (!WORD_REGISTER_OPERATIONS)
+	return 1;
+
       /* Likewise on machines that do, if the mode of the object is smaller
 	 than a word and loads of that size don't sign extend, we can say
 	 nothing about the high order bits.  */
@@ -4778,7 +4778,6 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
 #endif
 	  )
 	return 1;
-#endif
     }
 
   switch (code)
@@ -4857,7 +4856,6 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
 				   - bitwidth)));
 	}
 
-#ifdef WORD_REGISTER_OPERATIONS
 #ifdef LOAD_EXTEND_OP
       /* For paradoxical SUBREGs on machines where all register operations
 	 affect the entire register, just look inside.  Note that we are
@@ -4869,13 +4867,13 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x,
 	 then we lose all sign bit copies that existed before the store
 	 to the stack.  */
 
-      if (paradoxical_subreg_p (x)
+      if (WORD_REGISTER_OPERATIONS
+	  && paradoxical_subreg_p (x)
 	  && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
 	  && MEM_P (SUBREG_REG (x)))
 	return cached_num_sign_bit_copies (SUBREG_REG (x), mode,
 					   known_x, known_mode, known_ret);
 #endif
-#endif
       break;
 
     case SIGN_EXTRACT:
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 0901aafe25f..aeca187d83f 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -673,9 +673,7 @@ simplify_truncation (machine_mode mode, rtx op,
      the truncation, i.e. simplify (truncate:QI (op:SI (x:SI) (y:SI))) into
      (op:QI (truncate:QI (x:SI)) (truncate:QI (y:SI))).  */
   if (1
-#ifdef WORD_REGISTER_OPERATIONS
-      && precision >= BITS_PER_WORD
-#endif
+      && (!WORD_REGISTER_OPERATIONS || precision >= BITS_PER_WORD)
       && (GET_CODE (op) == PLUS
 	  || GET_CODE (op) == MINUS
 	  || GET_CODE (op) == MULT))