diff options
| author | gretay <gretay@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-04-19 12:55:26 +0000 |
|---|---|---|
| committer | gretay <gretay@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-04-19 12:55:26 +0000 |
| commit | a5c5144fad3f41434f0bbde85007ec3882ad4ce3 (patch) | |
| tree | d427346b6e92609757c00d5e5ee52467426b530e /gcc | |
| parent | d359df0c0eeff7ac4e3f1fb17d61741fa32e29e1 (diff) | |
| download | gcc-a5c5144fad3f41434f0bbde85007ec3882ad4ce3.tar.gz | |
2013-04-19 Greta Yorsh <Greta.Yorsh@arm.com>
PR target/56797
* config/arm/arm.c (load_multiple_sequence): Require SP
as base register for loads if SP is in the register list.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@198091 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 7 |
2 files changed, 13 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 43ed933b77a..439471d4d79 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2013-04-19 Greta Yorsh <Greta.Yorsh@arm.com> + + PR target/56797 + * config/arm/arm.c (load_multiple_sequence): Require SP + as base register for loads if SP is in the register list. + 2013-04-19 Martin Jambor <mjambor@suse.cz> PR tree-optimization/56718 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9088d1a64ab..7567afc719a 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -10755,6 +10755,13 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, || (i != nops - 1 && unsorted_regs[i] == base_reg)) return 0; + /* Don't allow SP to be loaded unless it is also the base + register. It guarantees that SP is reset correctly when + an LDM instruction is interruptted. Otherwise, we might + end up with a corrupt stack. */ + if (unsorted_regs[i] == SP_REGNUM && base_reg != SP_REGNUM) + return 0; + unsorted_offsets[i] = INTVAL (offset); if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) order[0] = i; |