summaryrefslogtreecommitdiff
path: root/gcc/testsuite
diff options
context:
space:
mode:
authoraldyh <aldyh@138bc75d-0d04-0410-961f-82ee72b054a4>2011-07-27 13:22:09 +0000
committeraldyh <aldyh@138bc75d-0d04-0410-961f-82ee72b054a4>2011-07-27 13:22:09 +0000
commit4bb60ec7c74253ba77870bceced0e3fb31cf39d2 (patch)
treeefd1ef13f8faacffa0a54f18314494501d46696b /gcc/testsuite
parent297effe4a0af07893bba126c94f447e91da63474 (diff)
downloadgcc-4bb60ec7c74253ba77870bceced0e3fb31cf39d2.tar.gz
* params.h (ALLOW_STORE_DATA_RACES): New.
* params.def (PARAM_ALLOW_STORE_DATA_RACES): New. * Makefile.in (expr.o): Depend on PARAMS_H. * machmode.h (get_best_mode): Add argument. * fold-const.c (optimize_bit_field_compare): Add argument to get_best_mode. (fold_truthop): Same. * ifcvt.c (noce_emit_move_insn): Add argument to store_bit_field. * expr.c (emit_group_store): Same. (copy_blkmode_from_reg): Same. (write_complex_part): Same. (optimize_bitfield_assignment_op): Add argument. Add argument to get_best_mode. (get_bit_range): New. (expand_assignment): Calculate maxbits and pass it down accordingly. (store_field): New argument. (expand_expr_real_2): New argument to store_field. Include params.h. * expr.h (store_bit_field): New argument. * stor-layout.c (get_best_mode): Restrict mode expansion by taking into account maxbits. * calls.c (store_unaligned_arguments_into_pseudos): New argument to store_bit_field. * expmed.c (store_bit_field_1): New argument. Use it. (store_bit_field): Same. (store_fixed_bit_field): Same. (store_split_bit_field): Same. (extract_bit_field_1): Pass new argument to get_best_mode. (extract_bit_field): Same. * stmt.c (store_bit_field): Pass new argument to store_bit_field. * doc/invoke.texi: Document parameter allow-store-data-races. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@176824 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/testsuite')
-rw-r--r--gcc/testsuite/c-c++-common/cxxbitfields-2.c19
-rw-r--r--gcc/testsuite/c-c++-common/cxxbitfields-3.c21
-rw-r--r--gcc/testsuite/c-c++-common/cxxbitfields-4.c18
-rw-r--r--gcc/testsuite/c-c++-common/cxxbitfields-5.c29
-rw-r--r--gcc/testsuite/c-c++-common/cxxbitfields.c18
5 files changed, 105 insertions, 0 deletions
diff --git a/gcc/testsuite/c-c++-common/cxxbitfields-2.c b/gcc/testsuite/c-c++-common/cxxbitfields-2.c
new file mode 100644
index 00000000000..b98b56daa91
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/cxxbitfields-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 --param allow-store-data-races=0" } */
+
+/* Test that we don't store past VAR.K. */
+
+struct S
+{
+ volatile int i;
+ volatile int j: 32;
+ volatile int k: 15;
+ volatile char c[2];
+} var;
+
+void setit()
+{
+ var.k = 13;
+}
+
+/* { dg-final { scan-assembler-not "movl.*, var" } } */
diff --git a/gcc/testsuite/c-c++-common/cxxbitfields-3.c b/gcc/testsuite/c-c++-common/cxxbitfields-3.c
new file mode 100644
index 00000000000..6fc4876f0ea
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/cxxbitfields-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 --param allow-store-data-races=0" } */
+
+/* Make sure we don't narrow down to a QI or HI to store into VAR.J,
+ but instead use an SI. */
+
+struct S
+{
+ volatile int i: 4;
+ volatile int j: 4;
+ volatile int k: 8;
+ volatile int l: 8;
+ volatile int m: 8;
+} var;
+
+void setit()
+{
+ var.j = 5;
+}
+
+/* { dg-final { scan-assembler "movl.*, var" } } */
diff --git a/gcc/testsuite/c-c++-common/cxxbitfields-4.c b/gcc/testsuite/c-c++-common/cxxbitfields-4.c
new file mode 100644
index 00000000000..a2d55f4a8c4
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/cxxbitfields-4.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 --param allow-store-data-races=0" } */
+
+struct bits
+{
+ char a;
+ int b:7;
+ int c:9;
+ unsigned char d;
+} x;
+
+/* Store into <c> should not clobber <d>. */
+void update_c(struct bits *p, int val)
+{
+ p -> c = val;
+}
+
+/* { dg-final { scan-assembler-not "movl" } } */
diff --git a/gcc/testsuite/c-c++-common/cxxbitfields-5.c b/gcc/testsuite/c-c++-common/cxxbitfields-5.c
new file mode 100644
index 00000000000..69e4e1067bf
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/cxxbitfields-5.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 --param allow-store-data-races=0" } */
+
+#include <stdlib.h>
+
+struct bits
+{
+ char a;
+ int b:7;
+ int c:9;
+ unsigned char d;
+} x;
+
+struct bits *p;
+
+static void allocit()
+{
+ p = (struct bits *) malloc (sizeof (struct bits));
+}
+
+/* Store into <c> should not clobber <d>. */
+/* We should not use a 32-bit move to store into p->, but a smaller move. */
+void foo()
+{
+ allocit();
+ p -> c = 55;
+}
+
+/* { dg-final { scan-assembler-not "movl\t\\(" } } */
diff --git a/gcc/testsuite/c-c++-common/cxxbitfields.c b/gcc/testsuite/c-c++-common/cxxbitfields.c
new file mode 100644
index 00000000000..43c840b15eb
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/cxxbitfields.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 --param allow-store-data-races=0" } */
+
+/* Test that we don't store past VAR.A. */
+
+struct S
+{
+ volatile unsigned int a : 4;
+ unsigned char b;
+ unsigned int c : 6;
+} var;
+
+void set_a()
+{
+ var.a = 12;
+}
+
+/* { dg-final { scan-assembler-not "movl.*, var" } } */