diff options
| author | vmakarov <vmakarov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-12-05 19:39:39 +0000 |
|---|---|---|
| committer | vmakarov <vmakarov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-12-05 19:39:39 +0000 |
| commit | 58f94f4a0937e15268040c4f3f9070f9a1a1a406 (patch) | |
| tree | 30b00583b50c51a9399730c4ded2beb237a26a04 /gcc/testsuite/gcc.target/mips | |
| parent | 583d5f6b1f6f0b63439649c6a0bc3dd8cdeb67d4 (diff) | |
| download | gcc-58f94f4a0937e15268040c4f3f9070f9a1a1a406.tar.gz | |
2013-12-05 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/59317
* lra-constraints.c (in_class_p): Don't ignore insn with constant
as a source.
2013-12-05 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/59317
* testsuite/gcc.target/mips/pr59317.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205718 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/testsuite/gcc.target/mips')
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/pr59317.c | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/mips/pr59317.c b/gcc/testsuite/gcc.target/mips/pr59317.c new file mode 100644 index 00000000000..dd23f7c8649 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr59317.c @@ -0,0 +1,83 @@ +/* { dg-do compile } */ +/* { dg-options "-mips16" } */ +extern void abort(); + +int i_0, i_1, i_2, i_3, i_4, i_5, i_6, i_7, i_8, i_9; +int j_0, j_1, j_2, j_3, j_4, j_5, j_6, j_7, j_8, j_9; + +int main() +{ + register int *x1 = &i_1; + register int *x2 = &i_2; + register int *x3 = &i_3; + register int *x4 = &i_4; + register int *x5 = &i_5; + register int *x6 = &i_6; + register int *x7 = &i_7; + register int *x8 = &i_8; + register int *x9 = &i_9; + + register int *y0 = &j_0; + register int *y1 = &j_1; + register int *y2 = &i_2; + register int *y3 = &j_3; + register int *y4 = &j_4; + register int *y5 = &j_5; + register int *y6 = &j_6; + register int *y7 = &j_7; + register int *y8 = &j_8; + register int *y9 = &j_9; + + asm volatile ("" : "=r" (x2) : "0" (x2)); + asm volatile ("" : "=r" (x3) : "0" (x3)); + asm volatile ("" : "=r" (x4) : "0" (x4)); + asm volatile ("" : "=r" (x5) : "0" (x5)); + asm volatile ("" : "=r" (x6) : "0" (x6)); + asm volatile ("" : "=r" (x7) : "0" (x7)); + asm volatile ("" : "=r" (x8) : "0" (x8)); + asm volatile ("" : "=r" (x9) : "0" (x9)); + + asm volatile ("" : "=r" (y0) : "0" (y0)); + asm volatile ("" : "=r" (y1) : "0" (y1)); + asm volatile ("" : "=r" (y2) : "0" (y2)); + asm volatile ("" : "=r" (y3) : "0" (y3)); + asm volatile ("" : "=r" (y4) : "0" (y4)); + asm volatile ("" : "=r" (y5) : "0" (y5)); + asm volatile ("" : "=r" (y6) : "0" (y6)); + asm volatile ("" : "=r" (y7) : "0" (y7)); + asm volatile ("" : "=r" (y8) : "0" (y8)); + asm volatile ("" : "=r" (y9) : "0" (y9)); + + asm volatile ("" : "=r" (x1) : "0" (x1)); + asm volatile ("" : "=r" (x2) : "0" (x2)); + asm volatile ("" : "=r" (x3) : "0" (x3)); + asm volatile ("" : "=r" (x4) : "0" (x4)); + asm volatile ("" : "=r" (x5) : "0" (x5)); + asm volatile ("" : "=r" (x6) : "0" (x6)); + asm volatile ("" : "=r" (x7) : "0" (x7)); + asm volatile ("" : "=r" (x8) : "0" (x8)); + asm volatile ("" : "=r" (x9) : "0" (x9)); + + asm volatile ("" : "=r" (y0) : "0" (y0)); + asm volatile ("" : "=r" (y1) : "0" (y1)); + asm volatile ("" : "=r" (y2) : "0" (y2)); + asm volatile ("" : "=r" (y3) : "0" (y3)); + asm volatile ("" : "=r" (y4) : "0" (y4)); + asm volatile ("" : "=r" (y5) : "0" (y5)); + asm volatile ("" : "=r" (y6) : "0" (y6)); + asm volatile ("" : "=r" (y7) : "0" (y7)); + asm volatile ("" : "=r" (y8) : "0" (y8)); + asm volatile ("" : "=r" (y9) : "0" (y9)); + + if (y0 != &j_0) abort (); + if (y1 != &j_1) abort (); + if (y2 != &j_2) abort (); + if (y3 != &j_3) abort (); + if (y4 != &j_4) abort (); + if (y5 != &j_5) abort (); + if (y6 != &j_6) abort (); + if (y7 != &j_7) abort (); + if (y8 != &j_8) abort (); + if (y9 != &j_9) abort (); + return 0; +} |