* gcc.misc-tests/i386-prefetch.exp: New.

	* gcc.misc-tests/i386-pf-3dnow-1.c: New test.
	* gcc.misc-tests/i386-pf-athlon-1.c: New test.
	* gcc.misc-tests/i386-pf-none-1.c: New test.
	* gcc.misc-tests/i386-pf-sse-1.c: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@48876 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 94 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.misc-tests/i386-prefetch.exp b/gcc/testsuite/gcc.misc-tests/i386-prefetch.exp
new file mode 100644
index 00000000000..353a1e6f1f9
--- /dev/null
+++ b/gcc/testsuite/gcc.misc-tests/i386-prefetch.exp
@@ -0,0 +1,94 @@
+#   Copyright (C) 2002 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+
+# Test that the correct data prefetch instructions (SSE or 3DNow! variant,
+# or none) are used for various i386 cpu-type and instruction set
+# extension options for __builtin_prefetch.
+
+# Failure reports do not include the compile option that was used; that
+# information can be seen in the compile line in the log file.
+
+# Do not generate prefetch instructions for the following options.
+
+set PREFETCH_NONE [list \
+	{ -mcpu=i386 } \
+	{ -mcpu=i486 } \
+	{ -mcpu=i586 } \
+	{ -mcpu=i686 } \
+	{ -mcpu=pentium2 } \
+	{ -mcpu=k6 } \
+	{ -mcpu=k6-2 } \
+	{ -mcpu=k6-3 } \
+	{ -march=i386 } \
+	{ -march=i486 } \
+	{ -march=i586 } \
+	{ -march=i686 } \
+	{ -march=pentium2 } \
+	{ -march=k6 } ]
+
+# For options in PREFETCH_SSE, generate SSE prefetch instructions for
+# __builtin_prefetch.  This includes -mcpu for targets that treat prefetch
+# instructions as nops.
+
+set PREFETCH_SSE [list \
+	{ -mcpu=pentium3 } \
+	{ -mcpu=pentium4 } \
+	{ -mcpu=athlon } \
+	{ -mcpu=athlon-4 } \
+	{ -march=pentium3 } \
+	{ -march=pentium4 } ]
+
+# Generate 3DNow! prefetch instructions for the following.
+
+set PREFETCH_3DNOW [list \
+	{ -march=k6-2 } \
+	{ -march=k6-3 } ]
+
+# Athlon supports both 3DNow! and SSE prefetch instructions.  For
+# __builtin_prefetch, generate the 3DNow! instruction for write
+# prefetches but SSE prefetch instructions for read prefetches.
+
+set PREFETCH_ATHLON [list \
+	{ -march=athlon } \
+	{ -march=athlon-4 } ]
+
+if $tracelevel then {
+    strace $tracelevel
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Initialize harness.
+dg-init
+
+set torture_with_loops $PREFETCH_NONE
+set torture_without_loops $PREFETCH_NONE
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/i386-pf-none-*.c]] ""
+
+set torture_with_loops $PREFETCH_SSE
+set torture_without_loops $PREFETCH_SSE
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/i386-pf-sse-*.c]] ""
+
+set torture_with_loops $PREFETCH_3DNOW
+set torture_without_loops $PREFETCH_3DNOW
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/i386-pf-3dnow-*.c]] ""
+
+set torture_with_loops $PREFETCH_ATHLON
+set torture_without_loops $PREFETCH_ATHLON
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/i386-pf-athlon-*.c]] ""
+
+dg-finish