[AArch64] Enable CCMP support for AArch64, PR64015 resolved

gcc/
2015-01-16  Zhenqiang Chen  <zhenqiang.chen@arm.com>

	PR target/64015
	* ccmp.c (expand_ccmp_next): New function.
	(expand_ccmp_expr_1, expand_ccmp_expr): Handle operand insn sequence
	and compare insn sequence.
	* config/aarch64/aarch64.c (aarch64_code_to_ccmode,
	aarch64_gen_ccmp_first, aarch64_gen_ccmp_next): New functions.
	(TARGET_GEN_CCMP_FIRST, TARGET_GEN_CCMP_NEXT): New MICRO.
	* config/aarch64/aarch64.md (*ccmp_and): Changed to ccmp_and<mode>.
	(*ccmp_ior): Changed to ccmp_ior<mode>.
	(cmp<mode>): New pattern.
	* doc/tm.texi (TARGET_GEN_CCMP_FIRST, TARGET_GEN_CCMP_NEXT): Update
	parameters.
	* target.def (gen_ccmp_first, gen_ccmp_next): Update parameters.

gcc/testsuite/
2015-01-16  Zhenqiang Chen <zhenqiang.chen@arm.com>

	* gcc.dg/pr64015.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219723 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 16 insertions, 9 deletions

diff --git a/gcc/target.def b/gcc/target.def
index 4aebcfeddd2..356f7c1c9a4 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -2542,24 +2542,31 @@ modes and they have different conditional execution capability, such as ARM.",
 
 DEFHOOK
 (gen_ccmp_first,
- "This function emits a comparison insn for the first of a sequence of\n\
- conditional comparisions.  It returns a comparison expression appropriate\n\
- for passing to @code{gen_ccmp_next} or @code{cbranch_optab}.  @var{code} is\n\
+ "This function prepares to emit a comparison insn for the first compare in a\n\
+ sequence of conditional comparisions.  It returns a appropriate @code{CC}\n\
+ for passing to @code{gen_ccmp_next} or @code{cbranch_optab}.  The insns to\n\
+ prepare the compare are saved in @var{prep_seq} and the compare insns are\n\
+ saved in @var{gen_seq}.  They will be emitted when all the compares in the\n\
+ the conditional comparision are generated without error.  @var{code} is\n\
  the @code{rtx_code} of the compare for @var{op0} and @var{op1}.",
- rtx, (int code, rtx op0, rtx op1),
+ rtx, (rtx *prep_seq, rtx *gen_seq, int code, tree op0, tree op1),
  NULL)
 
 DEFHOOK
 (gen_ccmp_next,
- "This function emits a conditional comparison within a sequence of\n\
- conditional comparisons.  The @var{prev} expression is the result of a\n\
- prior call to @code{gen_ccmp_first} or @code{gen_ccmp_next}.  It may return\n\
- @code{NULL} if the combination of @var{prev} and this comparison is\n\
+ "This function prepare to emit a conditional comparison within a sequence of\n\
+ conditional comparisons.  It returns a appropriate @code{CC} for passing to\n\
+ @code{gen_ccmp_next} or @code{cbranch_optab}.  The insns to prepare the\n\
+ compare are saved in @var{prep_seq} and the compare insns are saved in\n\
+ @var{gen_seq}.  They will be emitted when all the compares in the conditional\n\
+ comparision are generated without error.  The @var{prev} expression is the\n\
+ result of a prior call to @code{gen_ccmp_first} or @code{gen_ccmp_next}.  It\n\
+ may return @code{NULL} if the combination of @var{prev} and this comparison is\n\
  not supported, otherwise the result must be appropriate for passing to\n\
  @code{gen_ccmp_next} or @code{cbranch_optab}.  @var{code} is the\n\
  @code{rtx_code} of the compare for @var{op0} and @var{op1}.  @var{bit_code}\n\
  is @code{AND} or @code{IOR}, which is the op on the two compares.",
- rtx, (rtx prev, int cmp_code, rtx op0, rtx op1, int bit_code),
+ rtx, (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code, tree op0, tree op1, int bit_code),
  NULL)
 
 /* Return a new value for loop unroll size.  */