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| author | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-04-27 14:38:10 +0000 |
|---|---|---|
| committer | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-04-27 14:38:10 +0000 |
| commit | 7c7788722af7a68ffa374f01fb9b9a82c4d02585 (patch) | |
| tree | b70dc1bae57d8dd8a731c09733e5c72bd0c35a6f /gcc/rtlanal.c | |
| parent | 8974b6253d0b7ee4b43eae3ca00fbce8d120917c (diff) | |
| download | gcc-7c7788722af7a68ffa374f01fb9b9a82c4d02585.tar.gz | |
[rtlanal.c] Convert conditional compilation on WORD_REGISTER_OPERATIONS
* rtlanal.c (nonzero_bits1): Convert preprocessor check
for WORD_REGISTER_OPERATIONS to runtime check.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@235512 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/rtlanal.c')
| -rw-r--r-- | gcc/rtlanal.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index b4dff86c0e9..0b6e1e0e38d 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -4584,13 +4584,14 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x, nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode, known_x, known_mode, known_ret); -#if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP) +#ifdef LOAD_EXTEND_OP /* If this is a typical RISC machine, we only have to worry about the way loads are extended. */ - if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND - ? val_signbit_known_set_p (inner_mode, nonzero) - : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) - || !MEM_P (SUBREG_REG (x))) + if (WORD_REGISTER_OPERATIONS + && ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND + ? val_signbit_known_set_p (inner_mode, nonzero) + : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) + || !MEM_P (SUBREG_REG (x)))) #endif { /* On many CISC machines, accessing an object in a wider mode |