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authorbstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4>2008-07-15 08:52:53 +0000
committerbstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4>2008-07-15 08:52:53 +0000
commite05ef402a2ebebf3461227723eca43cf692f9feb (patch)
treecc579327961d3afb754162e12de142a15a075e67 /gcc/reload.c
parentd33dc667ca63584d1369f1dd80ba2a112218b2c0 (diff)
downloadgcc-e05ef402a2ebebf3461227723eca43cf692f9feb.tar.gz
2008-07-15 Basile Starynkevitch <basile@starynkevitch.net>
MELT branch merged with trunk r137813 git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@137817 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/reload.c')
-rw-r--r--gcc/reload.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/reload.c b/gcc/reload.c
index e426d3634f6..5a128f9fb81 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -6049,7 +6049,6 @@ find_reloads_subreg_address (rtx x, int force_replace, int opnum,
unsigned inner_size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
int offset;
rtx orig = tem;
- enum machine_mode orig_mode = GET_MODE (orig);
int reloaded;
/* For big-endian paradoxical subregs, SUBREG_BYTE does not
@@ -6095,7 +6094,9 @@ find_reloads_subreg_address (rtx x, int force_replace, int opnum,
/* For some processors an address may be valid in the
original mode but not in a smaller mode. For
example, ARM accepts a scaled index register in
- SImode but not in HImode. find_reloads_address
+ SImode but not in HImode. Similarly, the address may
+ have been valid before the subreg offset was added,
+ but not afterwards. find_reloads_address
assumes that we pass it a valid address, and doesn't
force a reload. This will probably be fine if
find_reloads_address finds some reloads. But if it
@@ -6103,7 +6104,6 @@ find_reloads_subreg_address (rtx x, int force_replace, int opnum,
valid address into an invalid one. Check for that
here. */
if (reloaded != 1
- && strict_memory_address_p (orig_mode, XEXP (tem, 0))
&& !strict_memory_address_p (GET_MODE (tem),
XEXP (tem, 0)))
push_reload (XEXP (tem, 0), NULL_RTX, &XEXP (tem, 0), (rtx*) 0,