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author | Richard Sandiford <richard.sandiford@linaro.org> | 2017-11-05 17:19:35 +0000 |
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committer | Richard Sandiford <richard.sandiford@linaro.org> | 2017-11-05 17:19:35 +0000 |
commit | 648f8fc59b2cc39abd24f4c22388b346cdebcc31 (patch) | |
tree | 3a07eccc4c22b265261edd75c9ec3910d9c626f5 /gcc/optabs.c | |
parent | 7bef5b82e4109778a0988d20e19e1ed29dadd835 (diff) | |
parent | 8c089b5c15a7b35644750ca393f1e66071ad9aa9 (diff) | |
download | gcc-648f8fc59b2cc39abd24f4c22388b346cdebcc31.tar.gz |
Merge trunk into sve
Diffstat (limited to 'gcc/optabs.c')
-rw-r--r-- | gcc/optabs.c | 34 |
1 files changed, 24 insertions, 10 deletions
diff --git a/gcc/optabs.c b/gcc/optabs.c index a6635e15116..7b8c0f60c99 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -6329,10 +6329,10 @@ expand_atomic_compare_and_swap (rtx *ptarget_bool, rtx *ptarget_oval, return true; } -/* Generate asm volatile("" : : : "memory") as the memory barrier. */ +/* Generate asm volatile("" : : : "memory") as the memory blockage. */ static void -expand_asm_memory_barrier (void) +expand_asm_memory_blockage (void) { rtx asm_op, clob; @@ -6348,6 +6348,17 @@ expand_asm_memory_barrier (void) emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, asm_op, clob))); } +/* Do not propagate memory accesses across this point. */ + +static void +expand_memory_blockage (void) +{ + if (targetm.have_memory_blockage ()) + emit_insn (targetm.gen_memory_blockage ()); + else + expand_asm_memory_blockage (); +} + /* This routine will either emit the mem_thread_fence pattern or issue a sync_synchronize to generate a fence for memory model MEMMODEL. */ @@ -6359,14 +6370,14 @@ expand_mem_thread_fence (enum memmodel model) if (targetm.have_mem_thread_fence ()) { emit_insn (targetm.gen_mem_thread_fence (GEN_INT (model))); - expand_asm_memory_barrier (); + expand_memory_blockage (); } else if (targetm.have_memory_barrier ()) emit_insn (targetm.gen_memory_barrier ()); else if (synchronize_libfunc != NULL_RTX) emit_library_call (synchronize_libfunc, LCT_NORMAL, VOIDmode); else - expand_asm_memory_barrier (); + expand_memory_blockage (); } /* Emit a signal fence with given memory model. */ @@ -6377,7 +6388,7 @@ expand_mem_signal_fence (enum memmodel model) /* No machine barrier is required to implement a signal fence, but a compiler memory barrier must be issued, except for relaxed MM. */ if (!is_mm_relaxed (model)) - expand_asm_memory_barrier (); + expand_memory_blockage (); } /* This function expands the atomic load operation: @@ -6399,7 +6410,7 @@ expand_atomic_load (rtx target, rtx mem, enum memmodel model) struct expand_operand ops[3]; rtx_insn *last = get_last_insn (); if (is_mm_seq_cst (model)) - expand_asm_memory_barrier (); + expand_memory_blockage (); create_output_operand (&ops[0], target, mode); create_fixed_operand (&ops[1], mem); @@ -6407,7 +6418,7 @@ expand_atomic_load (rtx target, rtx mem, enum memmodel model) if (maybe_expand_insn (icode, 3, ops)) { if (!is_mm_relaxed (model)) - expand_asm_memory_barrier (); + expand_memory_blockage (); return ops[0].value; } delete_insns_since (last); @@ -6457,14 +6468,14 @@ expand_atomic_store (rtx mem, rtx val, enum memmodel model, bool use_release) { rtx_insn *last = get_last_insn (); if (!is_mm_relaxed (model)) - expand_asm_memory_barrier (); + expand_memory_blockage (); create_fixed_operand (&ops[0], mem); create_input_operand (&ops[1], val, mode); create_integer_operand (&ops[2], model); if (maybe_expand_insn (icode, 3, ops)) { if (is_mm_seq_cst (model)) - expand_asm_memory_barrier (); + expand_memory_blockage (); return const0_rtx; } delete_insns_since (last); @@ -7095,7 +7106,10 @@ maybe_legitimize_operand (enum insn_code icode, unsigned int opno, if (mode != VOIDmode && must_eq (trunc_int_for_mode (op->int_value, mode), op->int_value)) - goto input; + { + op->value = gen_int_mode (op->int_value, mode); + goto input; + } break; } return insn_operand_matches (icode, opno, op->value); |