Remove trailing white spaces

	* lra-assigns.c: Remove trailing white spaces.
	* lra-coalesce.c: Likewise.
	* lra-constraints.c: Likewise.
	* lra-eliminations.c: Likewise.
	* lra-int.h: Likewise.
	* lra-spills.c: Likewise.
	* lra.c: Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@192966 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 17 insertions, 17 deletions

diff --git a/gcc/lra.c b/gcc/lra.c
index 9c4e5bf5cfe..33f48d5d4e4 100644
--- a/gcc/lra.c
+++ b/gcc/lra.c
@@ -44,12 +44,12 @@ along with GCC; see the file COPYING3.	If not see
 
    Here is block diagram of LRA passes:
 
-	  ---------------------				    
-	 | Undo inheritance    |      ---------------	     --------------- 
+	  ---------------------
+	 | Undo inheritance    |      ---------------	     ---------------
 	 | for spilled pseudos)|     | Memory-memory |	    | New (and old) |
 	 | and splits (for     |<----| move coalesce |<-----|	 pseudos    |
 	 | pseudos got the     |      ---------------	    |	assignment  |
-  Start	 |  same  hard regs)   |			     --------------- 
+  Start	 |  same  hard regs)   |			     ---------------
     |	  ---------------------					    ^
     V		  |		 ----------------		    |
  -----------	  V		| Update virtual |		    |
@@ -63,7 +63,7 @@ along with GCC; see the file COPYING3.	If not see
 	|    to memory	 |<-------|    RTL     |--------->|  transformations  |
 	|  substitution	 |	  | transfor-  |	  |    in EBB scope   |
 	 ----------------	  |  mations   |	   -------------------
-		|		    ------------ 
+		|		    ------------
 		V
     -------------------------
    | Hard regs substitution, |
@@ -958,7 +958,7 @@ collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data,
       break;
     case CLOBBER:
       /* We treat clobber of non-operand hard registers as early
-	 clobber (the behavior is expected from asm).  */ 
+	 clobber (the behavior is expected from asm).  */
       list = collect_non_operand_hard_regs (&XEXP (op, 0), data,
 					    list, OP_OUT, true);
       break;
@@ -1055,7 +1055,7 @@ lra_set_insn_recog_data (rtx insn)
 	  if (nop > 0)
 	    {
 	      const char *p =  recog_data.constraints[0];
-	      
+
 	      for (p =	constraints[0]; *p; p++)
 		n += *p == ',';
 	    }
@@ -1241,7 +1241,7 @@ lra_update_insn_recog_data (rtx insn)
   int n;
   unsigned int uid = INSN_UID (insn);
   struct lra_static_insn_data *insn_static_data;
-  
+
   check_and_expand_insn_recog_data (uid);
   if ((data = lra_insn_recog_data[uid]) != NULL
       && data->icode != INSN_CODE (insn))
@@ -1310,7 +1310,7 @@ lra_update_insn_recog_data (rtx insn)
       {
 	int i;
 	bool *bp;
-	
+
 	n = insn_static_data->n_alternatives;
 	bp = data->alternative_enabled_p;
 	lra_assert (n >= 0 && bp != NULL);
@@ -1578,7 +1578,7 @@ add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid,
       break;
     case CLOBBER:
       /* We treat clobber of non-operand hard registers as early
-	 clobber (the behavior is expected from asm).  */ 
+	 clobber (the behavior is expected from asm).  */
       add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_OUT, true);
       break;
     case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
@@ -2026,7 +2026,7 @@ check_rtl (bool final_p)
 	for (i = 0; i < id->insn_static_data->n_operands; i++)
 	  {
 	    rtx op = *id->operand_loc[i];
-	      
+
 	    if (MEM_P (op)
 		&& (GET_MODE (op) != BLKmode
 		    || GET_CODE (XEXP (op, 0)) != SCRATCH)
@@ -2055,7 +2055,7 @@ has_nonexceptional_receiver (void)
   /* If we're not optimizing, then just err on the safe side.  */
   if (!optimize)
     return true;
-  
+
   /* First determine which blocks can reach exit via normal paths.  */
   tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
 
@@ -2065,7 +2065,7 @@ has_nonexceptional_receiver (void)
   /* Place the exit block on our worklist.  */
   EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
   *tos++ = EXIT_BLOCK_PTR;
-  
+
   /* Iterate: find everything reachable from what we've already seen.  */
   while (tos != worklist)
     {
@@ -2155,17 +2155,17 @@ update_inc_notes (void)
 /* Set to 1 while in lra.  */
 int lra_in_progress;
 
-/* Start of reload pseudo regnos before the new spill pass.  */ 
+/* Start of reload pseudo regnos before the new spill pass.  */
 int lra_constraint_new_regno_start;
 
-/* Inheritance pseudo regnos before the new spill pass.	 */ 
+/* Inheritance pseudo regnos before the new spill pass.	 */
 bitmap_head lra_inheritance_pseudos;
 
-/* Split regnos before the new spill pass.  */ 
+/* Split regnos before the new spill pass.  */
 bitmap_head lra_split_regs;
 
 /* Reload pseudo regnos before the new assign pass which still can be
-   spilled after the assinment pass.  */ 
+   spilled after the assinment pass.  */
 bitmap_head lra_optional_reload_pseudos;
 
 /* First UID of insns generated before a new spill pass.  */
@@ -2307,7 +2307,7 @@ lra (FILE *f)
 	  else
 	    {
 	      /* Do coalescing only for regular algorithms.  */
-	      if (! lra_assign () && lra_coalesce ())	
+	      if (! lra_assign () && lra_coalesce ())
 		live_p = false;
 	      if (lra_undo_inheritance ())
 		live_p = false;