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| author | erich <erich@138bc75d-0d04-0410-961f-82ee72b054a4> | 1994-07-01 20:32:09 +0000 |
|---|---|---|
| committer | erich <erich@138bc75d-0d04-0410-961f-82ee72b054a4> | 1994-07-01 20:32:09 +0000 |
| commit | d31602da50ff731fec7fcdd7509845e660e052bb (patch) | |
| tree | feeab3c422df62284bb0cb9b03f9d82ab130feb1 /gcc/longlong.h | |
| parent | 2db03be87e5c72ed5c7fc71d9e50899f0d51605c (diff) | |
| download | gcc-d31602da50ff731fec7fcdd7509845e660e052bb.tar.gz | |
(arm umul_ppm): Fix typos in last change. Mark hard-coded
registers with "%|".
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@7634 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/longlong.h')
| -rw-r--r-- | gcc/longlong.h | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/gcc/longlong.h b/gcc/longlong.h index 4b30d71e1f6..86dfb29ceb2 100644 --- a/gcc/longlong.h +++ b/gcc/longlong.h @@ -132,8 +132,8 @@ #if defined (__arm__) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ - __asm__ ("adds %1,%4,%5 - adc %0,%2,%3" \ + __asm__ ("adds %1, %4, %5 + adc %0, %2, %3" \ : "=r" ((USItype)(sh)), \ "=&r" ((USItype)(sl)) \ : "%r" ((USItype)(ah)), \ @@ -141,8 +141,8 @@ "%r" ((USItype)(al)), \ "rI" ((USItype)(bl))) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ - __asm__ ("subs %1,%4,%5 - sbc %0,%2,%3" \ + __asm__ ("subs %1, %4, %5 + sbc %0, %2, %3" \ : "=r" ((USItype)(sh)), \ "=&r" ((USItype)(sl)) \ : "r" ((USItype)(ah)), \ @@ -150,19 +150,19 @@ "r" ((USItype)(al)), \ "rI" ((USItype)(bl))) #define umul_ppmm(xh, xl, a, b) \ - __asm__ ("; Inlined umul_ppmm - mov r0,%2 lsr 16 - mov r2,%3 lsr 16 - bic r1,%2,r0 lsl 16 - bic r2,%3,r2 lsl 16 - mul %1,r1,r2 - mul r2,r0,r2 - mul r1,%0,r1 - mul %0,r0,%0 - adds r1,r2,r1 - addcs %0,%0,0x10000 - adds %1,%1,r1 lsl 16 - adc %0,%0,r1 lsr 16" \ + __asm__ ("%@ Inlined umul_ppmm + mov %|r0, %2, lsr #16 + mov %|r2, %3, lsr #16 + bic %|r1, %2, %|r0, lsl #16 + bic %|r2, %3, %|r2, lsl #16 + mul %1, %|r1, %|r2 + mul %|r2, %|r0, %|r2 + mul %|r1, %0, %|r1 + mul %0, %|r0, %0 + adds %|r1, %|r2, %|r1 + addcs %0, %0, #65536 + adds %1, %1, %|r1, lsl #16 + adc %0, %0, %|r1, lsr #16" \ : "=&r" ((USItype)(xh)), \ "=r" ((USItype)(xl)) \ : "r" ((USItype)(a)), \ |