diff options
| author | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-02-12 16:30:53 +0000 |
|---|---|---|
| committer | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-02-12 16:30:53 +0000 |
| commit | 8b21beb20e34549be88451e0c4fec6bd6badb881 (patch) | |
| tree | a9970b42c2ad08d6a0e408e9b647d6568ed8bd41 /gcc/longlong.h | |
| parent | b899e8082e094e13abed789b586b4751cac97c96 (diff) | |
| download | gcc-8b21beb20e34549be88451e0c4fec6bd6badb881.tar.gz | |
gcc/
2009-02-12 Uros Bizjak <ubizjak@gmail.com>
* longlong.h (sub_ddmmss): New for ia64. Ported from GMP 4.2.
(umul_ppmm): Likewise.
(count_leading_zeros): Likewise.
(count_trailing_zeros): Likewise.
(UMUL_TIME): Likewise.
2009-02-12 H.J. Lu <hongjiu.lu@intel.com>
* config.gcc: Add ia64/t-fprules-softfp soft-fp/t-softfp to
tmake_file for ia64*-*-linux*.
* config/ia64/ia64.c (ia64_soft_fp_init_libfuncs): New.
(ia64_expand_compare): Use HPUX library for TFmode only for
HPUX.
(ia64_builtins): Add IA64_BUILTIN_COPYSIGNQ, IA64_BUILTIN_FABSQ
and IA64_BUILTIN_INFQ.
(ia64_init_builtins): Initialize __builtin_infq,
__builtin_fabsq and __builtin_copysignq if not HPUX.
(ia64_expand_builtin): Handle IA64_BUILTIN_COPYSIGNQ,
IA64_BUILTIN_FABSQ and IA64_BUILTIN_INFQ.
* config/ia64/lib1funcs.asm (__divtf3): Define only if
SHARED is defined.
(__fixtfti): Likewise.
(__fixunstfti): Likewise.
(__floattitf): Likewise.
* config/ia64/libgcc-glibc.ver: New.
* config/ia64/t-fprules-softfp: Likewise.
* config/ia64/sfp-machine.h: Likewise.
* config/ia64/linux.h (LIBGCC2_HAS_TF_MODE): New.
(LIBGCC2_TF_CEXT): Likewise.
(TF_SIZE): Likewise.
(TARGET_INIT_LIBFUNCS): Likewise.
* config/ia64/t-glibc: Add $(srcdir)/config/ia64/libgcc-glibc.ver
to SHLIB_MAPFILES.
libgcc/
2009-02-12 H.J. Lu <hongjiu.lu@intel.com>
* config.host: Add ia64/t-fprules-softfp ia64/t-softfp-compat
to tmake_file for ia64*-*-linux*.
* Makefile.in (gen-hide-list): Ignore .*_compat and .*@.*.
* config/ia64/__divxf3.asm: New.
* config/ia64/_fixtfdi.asm: Likewise.
* config/ia64/_fixunstfdi.asm: Likewise.
* config/ia64/_floatditf.asm: Likewise.
* config/ia64/t-fprules-softfp: Likewise.
* config/ia64/t-softfp-compat: Likewise.
* config/ia64/tf-signs.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@144130 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/longlong.h')
| -rw-r--r-- | gcc/longlong.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/gcc/longlong.h b/gcc/longlong.h index 9bfd322d59f..57308bd9b79 100644 --- a/gcc/longlong.h +++ b/gcc/longlong.h @@ -432,6 +432,55 @@ UDItype __umulsidi3 (USItype, USItype); __w; }) #endif /* __i960__ */ +#if defined (__ia64) && W_TYPE_SIZE == 64 +/* This form encourages gcc (pre-release 3.4 at least) to emit predicated + "sub r=r,r" and "sub r=r,r,1", giving a 2 cycle latency. The generic + code using "al<bl" arithmetically comes out making an actual 0 or 1 in a + register, which takes an extra cycle. */ +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + do { \ + UWtype __x; \ + __x = (al) - (bl); \ + if ((al) < (bl)) \ + (sh) = (ah) - (bh) - 1; \ + else \ + (sh) = (ah) - (bh); \ + (sl) = __x; \ + } while (0) + +/* Do both product parts in assembly, since that gives better code with + all gcc versions. Some callers will just use the upper part, and in + that situation we waste an instruction, but not any cycles. */ +#define umul_ppmm(ph, pl, m0, m1) \ + __asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0" \ + : "=&f" (ph), "=f" (pl) \ + : "f" (m0), "f" (m1)) +#define count_leading_zeros(count, x) \ + do { \ + UWtype _x = (x), _y, _a, _c; \ + __asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x)); \ + __asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y)); \ + _c = (_a - 1) << 3; \ + _x >>= _c; \ + if (_x >= 1 << 4) \ + _x >>= 4, _c += 4; \ + if (_x >= 1 << 2) \ + _x >>= 2, _c += 2; \ + _c += _x >> 1; \ + (count) = W_TYPE_SIZE - 1 - _c; \ + } while (0) +/* similar to what gcc does for __builtin_ffs, but 0 based rather than 1 + based, and we don't need a special case for x==0 here */ +#define count_trailing_zeros(count, x) \ + do { \ + UWtype __ctz_x = (x); \ + __asm__ ("popcnt %0 = %1" \ + : "=r" (count) \ + : "r" ((__ctz_x-1) & ~__ctz_x)); \ + } while (0) +#define UMUL_TIME 14 +#endif + #if defined (__M32R__) && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ /* The cmp clears the condition bit. */ \ |