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authorebotcazou <ebotcazou@138bc75d-0d04-0410-961f-82ee72b054a4>2010-10-13 21:43:42 +0000
committerebotcazou <ebotcazou@138bc75d-0d04-0410-961f-82ee72b054a4>2010-10-13 21:43:42 +0000
commit58611ff144185923830ea254cbb0655b3a3ecdb4 (patch)
treebdb90237b6cec0a8cd6c6ba17503d4263d5cbe5f /gcc/ira-costs.c
parent8cedf886c61647fb0f96cdecd3e03a69cd5faea3 (diff)
downloadgcc-58611ff144185923830ea254cbb0655b3a3ecdb4.tar.gz
PR rtl-optimization/45912
* ira-costs.c (ira_tune_allocno_costs_and_cover_classes): Test the regno of registers instead of their index to compute the alignment. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@165437 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/ira-costs.c')
-rw-r--r--gcc/ira-costs.c19
1 files changed, 9 insertions, 10 deletions
diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index 3d8298d94a0..db9ed7cd03d 100644
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -1789,15 +1789,14 @@ ira_tune_allocno_costs_and_cover_classes (void)
if (min_cost != INT_MAX)
ALLOCNO_COVER_CLASS_COST (a) = min_cost;
- /* Some targets allow pseudos to be allocated to unaligned
- sequences of hard registers. However, selecting an unaligned
- sequence can unnecessarily restrict later allocations. So
- increase the cost of unaligned hard regs to encourage the use
- of aligned hard regs. */
+ /* Some targets allow pseudos to be allocated to unaligned sequences
+ of hard registers. However, selecting an unaligned sequence can
+ unnecessarily restrict later allocations. So increase the cost of
+ unaligned hard regs to encourage the use of aligned hard regs. */
{
- int nregs, index;
+ const int nregs = ira_reg_class_nregs[cover_class][ALLOCNO_MODE (a)];
- if ((nregs = ira_reg_class_nregs[cover_class][ALLOCNO_MODE (a)]) > 1)
+ if (nregs > 1)
{
ira_allocate_and_set_costs
(&ALLOCNO_HARD_REG_COSTS (a), cover_class,
@@ -1805,10 +1804,10 @@ ira_tune_allocno_costs_and_cover_classes (void)
reg_costs = ALLOCNO_HARD_REG_COSTS (a);
for (j = n - 1; j >= 0; j--)
{
- if (j % nregs != 0)
+ regno = ira_non_ordered_class_hard_regs[cover_class][j];
+ if ((regno % nregs) != 0)
{
- regno = ira_non_ordered_class_hard_regs[cover_class][j];
- index = ira_class_hard_reg_index[cover_class][regno];
+ int index = ira_class_hard_reg_index[cover_class][regno];
ira_assert (index != -1);
reg_costs[index] += ALLOCNO_FREQ (a);
}