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author | law <law@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-04-03 15:29:41 +0000 |
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committer | law <law@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-04-03 15:29:41 +0000 |
commit | 416700dcb6099d38685af39c625c187282c99f2d (patch) | |
tree | 2b992d75cb0febac853d6e478477ea1521048402 /gcc/gcc.texi | |
parent | ef8b109f27bfcab514220c1b815e9bbb8cbdc11d (diff) | |
download | gcc-416700dcb6099d38685af39c625c187282c99f2d.tar.gz |
* gcc.texi: Add info on regmove pass
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@26160 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/gcc.texi')
-rw-r--r-- | gcc/gcc.texi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/gcc/gcc.texi b/gcc/gcc.texi index 4f9ceeb4ea8..16828160c32 100644 --- a/gcc/gcc.texi +++ b/gcc/gcc.texi @@ -3458,6 +3458,18 @@ The option @samp{-dc} causes a debugging dump of the RTL code after this pass. This dump file's name is made by appending @samp{.combine} to the input file name. +@cindex register movement +@item +Register movement (@file{regmove.c}). This pass looks for cases where +matching constraints would force an instruction to need a reload, and +this reload would be a register to register move. It them attempts +to change the registers used by the instruction to avoid the move +instruction. + +The option @samp{-dN} causes a debugging dump of the RTL code after +this pass. This dump file's name is made by appending @samp{.regmove} +to the input file name. + @cindex instruction scheduling @cindex scheduling, instruction @item |