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| author | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-12-06 22:15:31 +0000 |
|---|---|---|
| committer | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-12-06 22:15:31 +0000 |
| commit | f887f8314a0fe76c0667bde7d7ea811e24d66359 (patch) | |
| tree | 4c41da816695dbf5956be6f8d316107c9af52dfe /gcc/dojump.c | |
| parent | ec4ed0ce392902b7fa938dad6aea89b65b1b86af (diff) | |
| download | gcc-f887f8314a0fe76c0667bde7d7ea811e24d66359.tar.gz | |
[gcc]
2016-12-06 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/78658
* config/rs6000/rs6000.md (zero_extendqi<mode>2): Use ^ instead of
?* constraints for the ISA 3.0 patterns, so the register allocator
is more likely to allocate QImode/HImode to vector registers for
conversion to floating point unless a reload is needed.
(zero_extendhi<mode>2): Likewise.
(float<QHI:mode><FP_ISA3:mode>2_internal): Properly deal with the
first alternative which is converting QImode/HImode to floating
point and the QImode/HImode value is in a vector register, and
does not allocate the second pseudo register. Remove zero
extending into traditional floating point registers, since the
instruction used only works on traditional altivec registers.
(floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
[gcc/testsuite]
2016-12-06 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/78658
* gcc.target/powerpc/pr78658.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243320 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/dojump.c')
0 files changed, 0 insertions, 0 deletions