* config.gcc: Add m32c-elf support.

* doc/contrib.texi: Mention m32c.
* doc/extend.texi: Document m32c extensions.
* doc/install.texi: Mention m32c.
* doc/invoke.texi: Document m32c options.
* doc/md.texi: Document m32c constraints.

* config/m32c/addsub.md: New file.
* config/m32c/bitops.md: New file.
* config/m32c/cond.md: New file.
* config/m32c/jump.md: New file.
* config/m32c/m32c-lib1.S: New file.
* config/m32c/m32c-lib2.c: New file.
* config/m32c/m32c-modes.def: New file.
* config/m32c/m32c-pragma.c: New file.
* config/m32c/m32c-protos.h: New file.
* config/m32c/m32c.abi: New file.
* config/m32c/m32c.c: New file.
* config/m32c/m32c.h: New file.
* config/m32c/m32c.md: New file.
* config/m32c/m32c.opt: New file.
* config/m32c/minmax.md: New file.
* config/m32c/mov.md: New file.
* config/m32c/muldiv.md: New file.
* config/m32c/predicates.md: New file.
* config/m32c/prologue.md: New file.
* config/m32c/shift.md: New file.
* config/m32c/t-m32c: New file.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@102207 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 197 insertions, 6 deletions

diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi
index beee30fb0f7..d4c71ecd76a 100644
--- a/gcc/doc/contrib.texi
+++ b/gcc/doc/contrib.texi
@@ -206,8 +206,8 @@ Bud Davis for work on the G77 and gfortran compilers.
 Mo DeJong for GCJ and libgcj bug fixes.
 
 @item
-DJ Delorie for the DJGPP port, build and libiberty maintenance, and
-various bug fixes.
+DJ Delorie for the DJGPP port, build and libiberty maintenance,
+various bug fixes, and the M32C port.
 
 @item
 Arnaud Desitter for helping to debug gfortran.
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index c5d4fd83300..69bd151f84b 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -1887,10 +1887,10 @@ this attribute to work correctly.
 
 @item interrupt
 @cindex interrupt handler functions
-Use this attribute on the ARM, AVR, C4x, M32R/D and Xstormy16 ports to indicate
-that the specified function is an interrupt handler.  The compiler will
-generate function entry and exit sequences suitable for use in an
-interrupt handler when this attribute is present.
+Use this attribute on the ARM, AVR, C4x, M32C, M32R/D and Xstormy16
+ports to indicate that the specified function is an interrupt handler.
+The compiler will generate function entry and exit sequences suitable
+for use in an interrupt handler when this attribute is present.
 
 Note, interrupt handlers for the Blackfin, m68k, H8/300, H8/300H, H8S, and
 SH processors can be specified via the @code{interrupt_handler} attribute.
@@ -8953,6 +8953,7 @@ for further explanation.
 
 @menu
 * ARM Pragmas::
+* M32C Pragmas::
 * RS/6000 and PowerPC Pragmas::
 * Darwin Pragmas::
 * Solaris Pragmas::
@@ -8984,6 +8985,21 @@ Do not affect the @code{long_call} or @code{short_call} attributes of
 subsequent functions.
 @end table
 
+@node M32C Pragmas
+@subsection M32C Pragmas
+
+@table @code
+@item memregs @var{number}
+@cindex pragma, memregs
+Overrides the command line option @code{-memregs=} for the current
+file.  Use with care!  This pragma must be before any function in the
+file, and mixing different memregs values in different objects may
+make them incompatible.  This pragma is useful when a
+performance-critical function uses a memreg for temporary values,
+as it may allow you to reduce the number of memregs used.
+
+@end table
+
 @node RS/6000 and PowerPC Pragmas
 @subsection RS/6000 and PowerPC Pragmas
 
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index c1b54630b26..ac046c7a7fa 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -2246,6 +2246,8 @@ GNU Compiler Collection on your machine.
 @item
 @uref{#iq2000-x-elf,,iq2000-*-elf}
 @item
+@uref{#m32c-x-elf,,m32c-*-elf}
+@item
 @uref{#m32r-x-elf,,m32r-*-elf}
 @item
 @uref{#m6811-elf,,m6811-elf}
@@ -3183,6 +3185,13 @@ applications.  There are no standard Unix configurations.
 @html
 <hr />
 @end html
+@heading @anchor{m32c-x-elf}m32c-*-elf
+Renesas M32C processor.
+This configuration is intended for embedded systems.
+
+@html
+<hr />
+@end html
 @heading @anchor{m32r-x-elf}m32r-*-elf
 Renesas M32R processor.
 This configuration is intended for embedded systems.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3fde0683694..45e2a25dc72 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -544,6 +544,9 @@ Objective-C and Objective-C++ Dialects}.
 -mno-flush-trap -mflush-trap=@var{number} @gol
 -G @var{num}}
 
+@emph{M32C Options}
+@gccoptlist{-mcpu=@var{cpu} -msim -memregs=@var{number}}
+
 @emph{M680x0 Options}
 @gccoptlist{-m68000  -m68020  -m68020-40  -m68020-60  -m68030  -m68040 @gol
 -m68060  -mcpu32  -m5200  -m68881  -mbitfield  -mc68000  -mc68020   @gol
@@ -6957,6 +6960,7 @@ platform.
 * HPPA Options::
 * i386 and x86-64 Options::
 * IA-64 Options::
+* M32C Options::
 * M32R/D Options::
 * M680x0 Options::
 * M68hc1x Options::
@@ -9371,6 +9375,39 @@ to 64 bits.  These are HP-UX specific flags.
 
 @end table
 
+@node M32C Options
+@subsection M32C Options
+@cindex M32C options
+
+@table @gcctabopt
+@item -mcpu=@var{name}
+@opindex mcpu=
+Select the CPU for which code is generated.  @var{name} may be one of
+@samp{r8c} for the R8C/Tiny series, @samp{m16c} for the M16C (up to
+/60) series, @samp{m32cm} for the M16C/80 series, or @samp{m32c} for
+the M32C/80 series.
+
+@item -msim
+@opindex msim
+Specifies that the program will be run on the simulator.  This causes
+an alternate runtime library to be linked in which supports, for
+example, file I/O.  You must not use this option when generating
+programs that will run on real hardware; you must provide your own
+runtime library for whatever I/O functions are needed.
+
+@item -memregs=@var{number}
+@opindex memregs=
+Specifies the number of memory-based pseudo-registers GCC will use
+during code generation.  These pseudo-registers will be used like real
+registers, so there is a tradeoff between GCC's ability to fit the
+code into available registers, and the performance penalty of using
+memory instead of registers.  Note that all modules in a program must
+be compiled with the same value for this option.  Because of that, you
+must not use this option with the default runtime libraries gcc
+builds.
+
+@end table
+
 @node M32R/D Options
 @subsection M32R/D Options
 @cindex M32R/D options
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index bf71b7a80ab..682269b0d16 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2165,6 +2165,135 @@ An integer constant with all bits set except exactly one.
 Any SYMBOL_REF.
 @end table
 
+@item M32C---@file{m32c.c}
+
+@item Rsp
+@itemx Rfb
+@itemx Rsb
+@samp{$sp}, @samp{$fb}, @samp{$sb}.
+
+@item Rcr
+Any control register, when they're 16 bits wide (nothing if control
+registers are 24 bits wide)
+
+@item Rcl
+Any control register, when they're 24 bits wide.
+
+@item R0w
+@itemx R1w
+@itemx R2w
+@itemx R3w
+$r0, $r1, $r2, $r3.
+
+@item R02
+$r0 or $r2, or $r2r0 for 32 bit values.
+
+@item R13
+$r1 or $r3, or $r3r1 for 32 bit values.
+
+@item Rdi
+A register that can hold a 64 bit value.
+
+@item Rhl
+$r0 or $r1 (registers with addressable high/low bytes)
+
+@item R23
+$r2 or $r3
+
+@item Raa
+Address registers
+
+@item Raw
+Address registers when they're 16 bits wide.
+
+@item Ral
+Address registers when they're 24 bits wide.
+
+@item Rqi
+Registers that can hold QI values.
+
+@item Rad
+Registers that can be used with displacements ($a0, $a1, $sb).
+
+@item Rsi
+Registers that can hold 32 bit values.
+
+@item Rhi
+Registers that can hold 16 bit values.
+
+@item Rhc
+Registers chat can hold 16 bit values, including all control
+registers.
+
+@item Rra
+$r0 through R1, plus $a0 and $a1.
+
+@item Rfl
+The flags register.
+
+@item Rmm
+The memory-based pseudo-registers $mem0 through $mem15.
+
+@item Rpi
+Registers that can hold pointers (16 bit registers for r8c, m16c; 24
+bit registers for m32cm, m32c).
+
+@item Rpa
+Matches multiple registers in a PARALLEL to form a larger register.
+Used to match function return values.
+
+@item Is3
+-8 @dots{} 7
+
+@item IS1
+-128 @dots{} 127
+
+@item IS2
+-32768 @dots{} 32767
+
+@item IU2
+0 @dots{} 65535
+
+@item In4
+-8 @dots{} -1 or 1 @dots{} 8
+
+@item In5
+-16 @dots{} -1 or 1 @dots{} 16
+
+@item In4
+-8 @dots{} -1 or 1 @dots{} 8
+
+@item IM2
+-65536 @dots{} -1
+
+@item Ilb
+An 8 bit value with exactly one bit set.
+
+@item Ilw
+A 16 bit value with exactly one bit set.
+
+@item Sd
+The common src/dest memory addressing modes.
+
+@item Sa
+Memory addressed using $a0 or $a1.
+
+@item Si
+Memory addressed with immediate addresses.
+
+@item Ss
+Memory addressed using the stack pointer ($sp).
+
+@item Sf
+Memory addressed using the frame base register ($fb).
+
+@item Ss
+Memory addressed using the small base register ($sb).
+
+@item S1
+$r1h
+
+
 @item MIPS---@file{mips.h}
 @table @code
 @item d