diff options
| author | mrs <mrs@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-01-03 23:45:56 +0000 |
|---|---|---|
| committer | mrs <mrs@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-01-03 23:45:56 +0000 |
| commit | fe644b69d013e77c7fc2db2a9863969d4f564561 (patch) | |
| tree | a2cb1398bd46b8decaea84f1b7de8c7cd35e6046 /gcc/doc | |
| parent | 90079d10dd355193fe289fa0bfcb0d7be880d45a (diff) | |
| parent | 04e0495a6da35f3b0bcedbd75908cb6e9ba8ff8f (diff) | |
| download | gcc-fe644b69d013e77c7fc2db2a9863969d4f564561.tar.gz | |
Merge in trunk.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/wide-int@206327 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/doc')
54 files changed, 1776 insertions, 336 deletions
diff --git a/gcc/doc/arm-acle-intrinsics.texi b/gcc/doc/arm-acle-intrinsics.texi new file mode 100644 index 00000000000..e68f4cd2017 --- /dev/null +++ b/gcc/doc/arm-acle-intrinsics.texi @@ -0,0 +1,55 @@ +@c Copyright (C) 2013-2014 Free Software Foundation, Inc. +@c This is part of the GCC manual. +@c For copying conditions, see the file gcc.texi. + +@subsubsection CRC32 intrinsics + +@itemize @bullet +@item uint32_t __crc32b (uint32_t, uint8_t) +@*@emph{Form of expected instruction(s):} @code{crc32b @var{r0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint32_t __crc32h (uint32_t, uint16_t) +@*@emph{Form of expected instruction(s):} @code{crc32h @var{r0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint32_t __crc32w (uint32_t, uint32_t) +@*@emph{Form of expected instruction(s):} @code{crc32w @var{r0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint32_t __crc32d (uint32_t, uint64_t) +@*@emph{Form of expected instruction(s):} Two @code{crc32w @var{r0}, @var{r0}, @var{r0}} +instructions for AArch32. One @code{crc32w @var{w0}, @var{w0}, @var{x0}} instruction for +AArch64. +@end itemize + +@itemize @bullet +@item uint32_t __crc32cb (uint32_t, uint8_t) +@*@emph{Form of expected instruction(s):} @code{crc32cb @var{r0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint32_t __crc32ch (uint32_t, uint16_t) +@*@emph{Form of expected instruction(s):} @code{crc32ch @var{r0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint32_t __crc32cw (uint32_t, uint32_t) +@*@emph{Form of expected instruction(s):} @code{crc32cw @var{r0}, @var{r0}, @var{r0}} +@end itemize + + +@itemize @bullet +@item uint32_t __crc32cd (uint32_t, uint64_t) +@*@emph{Form of expected instruction(s):} Two @code{crc32cw @var{r0}, @var{r0}, @var{r0}} +instructions for AArch32. One @code{crc32cw @var{w0}, @var{w0}, @var{x0}} instruction for +AArch64. +@end itemize diff --git a/gcc/doc/arm-neon-intrinsics.texi b/gcc/doc/arm-neon-intrinsics.texi index fcd6c0f5305..67f84e096a7 100644 --- a/gcc/doc/arm-neon-intrinsics.texi +++ b/gcc/doc/arm-neon-intrinsics.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2006-2013 Free Software Foundation, Inc. +@c Copyright (C) 2006-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -4079,6 +4079,12 @@ @subsubsection Vector shift right and insert @itemize @bullet +@item poly64x1_t vsri_n_p64 (poly64x1_t, poly64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet @item uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int) @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}} @end itemize @@ -4139,6 +4145,12 @@ @itemize @bullet +@item poly64x2_t vsriq_n_p64 (poly64x2_t, poly64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet @item uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int) @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}} @end itemize @@ -4203,6 +4215,12 @@ @subsubsection Vector shift left and insert @itemize @bullet +@item poly64x1_t vsli_n_p64 (poly64x1_t, poly64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet @item uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int) @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}} @end itemize @@ -4263,6 +4281,12 @@ @itemize @bullet +@item poly64x2_t vsliq_n_p64 (poly64x2_t, poly64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet @item uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int) @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}} @end itemize @@ -5071,6 +5095,11 @@ @subsubsection Create vector from literal bit pattern @itemize @bullet +@item poly64x1_t vcreate_p64 (uint64_t) +@end itemize + + +@itemize @bullet @item uint32x2_t vcreate_u32 (uint64_t) @end itemize @@ -5184,6 +5213,11 @@ @itemize @bullet +@item poly64x1_t vdup_n_p64 (poly64_t) +@end itemize + + +@itemize @bullet @item uint64x1_t vdup_n_u64 (uint64_t) @end itemize @@ -5194,6 +5228,11 @@ @itemize @bullet +@item poly64x2_t vdupq_n_p64 (poly64_t) +@end itemize + + +@itemize @bullet @item uint32x4_t vdupq_n_u32 (uint32_t) @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}} @end itemize @@ -5440,6 +5479,11 @@ @itemize @bullet +@item poly64x1_t vdup_lane_p64 (poly64x1_t, const int) +@end itemize + + +@itemize @bullet @item uint64x1_t vdup_lane_u64 (uint64x1_t, const int) @end itemize @@ -5504,6 +5548,11 @@ @itemize @bullet +@item poly64x2_t vdupq_lane_p64 (poly64x1_t, const int) +@end itemize + + +@itemize @bullet @item uint64x2_t vdupq_lane_u64 (uint64x1_t, const int) @end itemize @@ -5518,6 +5567,11 @@ @subsubsection Combining vectors @itemize @bullet +@item poly64x2_t vcombine_p64 (poly64x1_t, poly64x1_t) +@end itemize + + +@itemize @bullet @item uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t) @end itemize @@ -5577,6 +5631,11 @@ @subsubsection Splitting vectors @itemize @bullet +@item poly64x1_t vget_high_p64 (poly64x2_t) +@end itemize + + +@itemize @bullet @item uint32x2_t vget_high_u32 (uint32x4_t) @end itemize @@ -5686,6 +5745,11 @@ @itemize @bullet +@item poly64x1_t vget_low_p64 (poly64x2_t) +@end itemize + + +@itemize @bullet @item uint64x1_t vget_low_u64 (uint64x2_t) @end itemize @@ -6818,6 +6882,12 @@ @subsubsection Vector extract @itemize @bullet +@item poly64x1_t vext_p64 (poly64x1_t, poly64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}} +@end itemize + + +@itemize @bullet @item uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int) @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}} @end itemize @@ -6884,6 +6954,12 @@ @itemize @bullet +@item poly64x2_t vextq_p64 (poly64x2_t, poly64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}} +@end itemize + + +@itemize @bullet @item uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int) @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}} @end itemize @@ -7174,6 +7250,12 @@ @subsubsection Bit selection @itemize @bullet +@item poly64x1_t vbsl_p64 (uint64x1_t, poly64x1_t, poly64x1_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet @item uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t) @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}} @end itemize @@ -7240,6 +7322,12 @@ @itemize @bullet +@item poly64x2_t vbslq_p64 (uint64x2_t, poly64x2_t, poly64x2_t) +@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet @item uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t) @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}} @end itemize @@ -7646,6 +7734,12 @@ @subsubsection Element/structure loads, VLD1 variants @itemize @bullet +@item poly64x1_t vld1_p64 (const poly64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint32x2_t vld1_u32 (const uint32_t *) @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]} @end itemize @@ -7712,6 +7806,12 @@ @itemize @bullet +@item poly64x2_t vld1q_p64 (const poly64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint32x4_t vld1q_u32 (const uint32_t *) @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} @end itemize @@ -7832,6 +7932,12 @@ @itemize @bullet +@item poly64x1_t vld1_lane_p64 (const poly64_t *, poly64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int) @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} @end itemize @@ -7898,6 +8004,12 @@ @itemize @bullet +@item poly64x2_t vld1q_lane_p64 (const poly64_t *, poly64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int) @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} @end itemize @@ -7964,6 +8076,12 @@ @itemize @bullet +@item poly64x1_t vld1_dup_p64 (const poly64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint64x1_t vld1_dup_u64 (const uint64_t *) @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} @end itemize @@ -8030,6 +8148,12 @@ @itemize @bullet +@item poly64x2_t vld1q_dup_p64 (const poly64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint64x2_t vld1q_dup_u64 (const uint64_t *) @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]} @end itemize @@ -8046,6 +8170,12 @@ @subsubsection Element/structure stores, VST1 variants @itemize @bullet +@item void vst1_p64 (poly64_t *, poly64x1_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item void vst1_u32 (uint32_t *, uint32x2_t) @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]} @end itemize @@ -8112,6 +8242,12 @@ @itemize @bullet +@item void vst1q_p64 (poly64_t *, poly64x2_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item void vst1q_u32 (uint32_t *, uint32x4_t) @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]} @end itemize @@ -8232,6 +8368,12 @@ @itemize @bullet +@item void vst1_lane_p64 (poly64_t *, poly64x1_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item void vst1_lane_s64 (int64_t *, int64x1_t, const int) @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]} @end itemize @@ -8298,6 +8440,12 @@ @itemize @bullet +@item void vst1q_lane_p64 (poly64_t *, poly64x2_t, const int) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item void vst1q_lane_s64 (int64_t *, int64x2_t, const int) @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]} @end itemize @@ -8368,6 +8516,12 @@ @itemize @bullet +@item poly64x1x2_t vld2_p64 (const poly64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint64x1x2_t vld2_u64 (const uint64_t *) @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} @end itemize @@ -8578,6 +8732,12 @@ @itemize @bullet +@item poly64x1x2_t vld2_dup_p64 (const poly64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint64x1x2_t vld2_dup_u64 (const uint64_t *) @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} @end itemize @@ -8648,6 +8808,12 @@ @itemize @bullet +@item void vst2_p64 (poly64_t *, poly64x1x2_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item void vst2_u64 (uint64_t *, uint64x1x2_t) @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]} @end itemize @@ -8862,6 +9028,12 @@ @itemize @bullet +@item poly64x1x3_t vld3_p64 (const poly64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint64x1x3_t vld3_u64 (const uint64_t *) @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} @end itemize @@ -9072,6 +9244,12 @@ @itemize @bullet +@item poly64x1x3_t vld3_dup_p64 (const poly64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint64x1x3_t vld3_dup_u64 (const uint64_t *) @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]} @end itemize @@ -9142,6 +9320,12 @@ @itemize @bullet +@item void vst3_p64 (poly64_t *, poly64x1x3_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item void vst3_u64 (uint64_t *, uint64x1x3_t) @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} @end itemize @@ -9356,6 +9540,12 @@ @itemize @bullet +@item poly64x1x4_t vld4_p64 (const poly64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint64x1x4_t vld4_u64 (const uint64_t *) @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} @end itemize @@ -9566,6 +9756,12 @@ @itemize @bullet +@item poly64x1x4_t vld4_dup_p64 (const poly64_t *) +@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item uint64x1x4_t vld4_dup_u64 (const uint64_t *) @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} @end itemize @@ -9636,6 +9832,12 @@ @itemize @bullet +@item void vst4_p64 (poly64_t *, poly64x1x4_t) +@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} +@end itemize + + +@itemize @bullet @item void vst4_u64 (uint64_t *, uint64x1x4_t) @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]} @end itemize @@ -10286,27 +10488,27 @@ @subsubsection Reinterpret casts @itemize @bullet -@item poly8x8_t vreinterpret_p8_u32 (uint32x2_t) +@item poly8x8_t vreinterpret_p8_p16 (poly16x4_t) @end itemize @itemize @bullet -@item poly8x8_t vreinterpret_p8_u16 (uint16x4_t) +@item poly8x8_t vreinterpret_p8_f32 (float32x2_t) @end itemize @itemize @bullet -@item poly8x8_t vreinterpret_p8_u8 (uint8x8_t) +@item poly8x8_t vreinterpret_p8_p64 (poly64x1_t) @end itemize @itemize @bullet -@item poly8x8_t vreinterpret_p8_s32 (int32x2_t) +@item poly8x8_t vreinterpret_p8_s64 (int64x1_t) @end itemize @itemize @bullet -@item poly8x8_t vreinterpret_p8_s16 (int16x4_t) +@item poly8x8_t vreinterpret_p8_u64 (uint64x1_t) @end itemize @@ -10316,72 +10518,77 @@ @itemize @bullet -@item poly8x8_t vreinterpret_p8_u64 (uint64x1_t) +@item poly8x8_t vreinterpret_p8_s16 (int16x4_t) @end itemize @itemize @bullet -@item poly8x8_t vreinterpret_p8_s64 (int64x1_t) +@item poly8x8_t vreinterpret_p8_s32 (int32x2_t) @end itemize @itemize @bullet -@item poly8x8_t vreinterpret_p8_f32 (float32x2_t) +@item poly8x8_t vreinterpret_p8_u8 (uint8x8_t) @end itemize @itemize @bullet -@item poly8x8_t vreinterpret_p8_p16 (poly16x4_t) +@item poly8x8_t vreinterpret_p8_u16 (uint16x4_t) @end itemize @itemize @bullet -@item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t) +@item poly8x8_t vreinterpret_p8_u32 (uint32x2_t) @end itemize @itemize @bullet -@item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t) +@item poly16x4_t vreinterpret_p16_p8 (poly8x8_t) @end itemize @itemize @bullet -@item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t) +@item poly16x4_t vreinterpret_p16_f32 (float32x2_t) @end itemize @itemize @bullet -@item poly8x16_t vreinterpretq_p8_s32 (int32x4_t) +@item poly16x4_t vreinterpret_p16_p64 (poly64x1_t) @end itemize @itemize @bullet -@item poly8x16_t vreinterpretq_p8_s16 (int16x8_t) +@item poly16x4_t vreinterpret_p16_s64 (int64x1_t) @end itemize @itemize @bullet -@item poly8x16_t vreinterpretq_p8_s8 (int8x16_t) +@item poly16x4_t vreinterpret_p16_u64 (uint64x1_t) @end itemize @itemize @bullet -@item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t) +@item poly16x4_t vreinterpret_p16_s8 (int8x8_t) @end itemize @itemize @bullet -@item poly8x16_t vreinterpretq_p8_s64 (int64x2_t) +@item poly16x4_t vreinterpret_p16_s16 (int16x4_t) @end itemize @itemize @bullet -@item poly8x16_t vreinterpretq_p8_f32 (float32x4_t) +@item poly16x4_t vreinterpret_p16_s32 (int32x2_t) @end itemize @itemize @bullet -@item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t) +@item poly16x4_t vreinterpret_p16_u8 (uint8x8_t) +@end itemize + + +@itemize @bullet +@item poly16x4_t vreinterpret_p16_u16 (uint16x4_t) @end itemize @@ -10391,792 +10598,1152 @@ @itemize @bullet -@item poly16x4_t vreinterpret_p16_u16 (uint16x4_t) +@item float32x2_t vreinterpret_f32_p8 (poly8x8_t) @end itemize @itemize @bullet -@item poly16x4_t vreinterpret_p16_u8 (uint8x8_t) +@item float32x2_t vreinterpret_f32_p16 (poly16x4_t) @end itemize @itemize @bullet -@item poly16x4_t vreinterpret_p16_s32 (int32x2_t) +@item float32x2_t vreinterpret_f32_p64 (poly64x1_t) @end itemize @itemize @bullet -@item poly16x4_t vreinterpret_p16_s16 (int16x4_t) +@item float32x2_t vreinterpret_f32_s64 (int64x1_t) @end itemize @itemize @bullet -@item poly16x4_t vreinterpret_p16_s8 (int8x8_t) +@item float32x2_t vreinterpret_f32_u64 (uint64x1_t) @end itemize @itemize @bullet -@item poly16x4_t vreinterpret_p16_u64 (uint64x1_t) +@item float32x2_t vreinterpret_f32_s8 (int8x8_t) @end itemize @itemize @bullet -@item poly16x4_t vreinterpret_p16_s64 (int64x1_t) +@item float32x2_t vreinterpret_f32_s16 (int16x4_t) @end itemize @itemize @bullet -@item poly16x4_t vreinterpret_p16_f32 (float32x2_t) +@item float32x2_t vreinterpret_f32_s32 (int32x2_t) @end itemize @itemize @bullet -@item poly16x4_t vreinterpret_p16_p8 (poly8x8_t) +@item float32x2_t vreinterpret_f32_u8 (uint8x8_t) @end itemize @itemize @bullet -@item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t) +@item float32x2_t vreinterpret_f32_u16 (uint16x4_t) @end itemize @itemize @bullet -@item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t) +@item float32x2_t vreinterpret_f32_u32 (uint32x2_t) @end itemize @itemize @bullet -@item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t) +@item poly64x1_t vreinterpret_p64_p8 (poly8x8_t) @end itemize @itemize @bullet -@item poly16x8_t vreinterpretq_p16_s32 (int32x4_t) +@item poly64x1_t vreinterpret_p64_p16 (poly16x4_t) @end itemize @itemize @bullet -@item poly16x8_t vreinterpretq_p16_s16 (int16x8_t) +@item poly64x1_t vreinterpret_p64_f32 (float32x2_t) @end itemize @itemize @bullet -@item poly16x8_t vreinterpretq_p16_s8 (int8x16_t) +@item poly64x1_t vreinterpret_p64_s64 (int64x1_t) @end itemize @itemize @bullet -@item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t) +@item poly64x1_t vreinterpret_p64_u64 (uint64x1_t) @end itemize @itemize @bullet -@item poly16x8_t vreinterpretq_p16_s64 (int64x2_t) +@item poly64x1_t vreinterpret_p64_s8 (int8x8_t) @end itemize @itemize @bullet -@item poly16x8_t vreinterpretq_p16_f32 (float32x4_t) +@item poly64x1_t vreinterpret_p64_s16 (int16x4_t) @end itemize @itemize @bullet -@item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t) +@item poly64x1_t vreinterpret_p64_s32 (int32x2_t) @end itemize @itemize @bullet -@item float32x2_t vreinterpret_f32_u32 (uint32x2_t) +@item poly64x1_t vreinterpret_p64_u8 (uint8x8_t) @end itemize @itemize @bullet -@item float32x2_t vreinterpret_f32_u16 (uint16x4_t) +@item poly64x1_t vreinterpret_p64_u16 (uint16x4_t) @end itemize @itemize @bullet -@item float32x2_t vreinterpret_f32_u8 (uint8x8_t) +@item poly64x1_t vreinterpret_p64_u32 (uint32x2_t) @end itemize @itemize @bullet -@item float32x2_t vreinterpret_f32_s32 (int32x2_t) +@item int64x1_t vreinterpret_s64_p8 (poly8x8_t) @end itemize @itemize @bullet -@item float32x2_t vreinterpret_f32_s16 (int16x4_t) +@item int64x1_t vreinterpret_s64_p16 (poly16x4_t) @end itemize @itemize @bullet -@item float32x2_t vreinterpret_f32_s8 (int8x8_t) +@item int64x1_t vreinterpret_s64_f32 (float32x2_t) @end itemize @itemize @bullet -@item float32x2_t vreinterpret_f32_u64 (uint64x1_t) +@item int64x1_t vreinterpret_s64_p64 (poly64x1_t) @end itemize @itemize @bullet -@item float32x2_t vreinterpret_f32_s64 (int64x1_t) +@item int64x1_t vreinterpret_s64_u64 (uint64x1_t) @end itemize @itemize @bullet -@item float32x2_t vreinterpret_f32_p16 (poly16x4_t) +@item int64x1_t vreinterpret_s64_s8 (int8x8_t) @end itemize @itemize @bullet -@item float32x2_t vreinterpret_f32_p8 (poly8x8_t) +@item int64x1_t vreinterpret_s64_s16 (int16x4_t) @end itemize @itemize @bullet -@item float32x4_t vreinterpretq_f32_u32 (uint32x4_t) +@item int64x1_t vreinterpret_s64_s32 (int32x2_t) @end itemize @itemize @bullet -@item float32x4_t vreinterpretq_f32_u16 (uint16x8_t) +@item int64x1_t vreinterpret_s64_u8 (uint8x8_t) @end itemize @itemize @bullet -@item float32x4_t vreinterpretq_f32_u8 (uint8x16_t) +@item int64x1_t vreinterpret_s64_u16 (uint16x4_t) @end itemize @itemize @bullet -@item float32x4_t vreinterpretq_f32_s32 (int32x4_t) +@item int64x1_t vreinterpret_s64_u32 (uint32x2_t) @end itemize @itemize @bullet -@item float32x4_t vreinterpretq_f32_s16 (int16x8_t) +@item uint64x1_t vreinterpret_u64_p8 (poly8x8_t) @end itemize @itemize @bullet -@item float32x4_t vreinterpretq_f32_s8 (int8x16_t) +@item uint64x1_t vreinterpret_u64_p16 (poly16x4_t) @end itemize @itemize @bullet -@item float32x4_t vreinterpretq_f32_u64 (uint64x2_t) +@item uint64x1_t vreinterpret_u64_f32 (float32x2_t) @end itemize @itemize @bullet -@item float32x4_t vreinterpretq_f32_s64 (int64x2_t) +@item uint64x1_t vreinterpret_u64_p64 (poly64x1_t) @end itemize @itemize @bullet -@item float32x4_t vreinterpretq_f32_p16 (poly16x8_t) +@item uint64x1_t vreinterpret_u64_s64 (int64x1_t) @end itemize @itemize @bullet -@item float32x4_t vreinterpretq_f32_p8 (poly8x16_t) +@item uint64x1_t vreinterpret_u64_s8 (int8x8_t) @end itemize @itemize @bullet -@item int64x1_t vreinterpret_s64_u32 (uint32x2_t) +@item uint64x1_t vreinterpret_u64_s16 (int16x4_t) @end itemize @itemize @bullet -@item int64x1_t vreinterpret_s64_u16 (uint16x4_t) +@item uint64x1_t vreinterpret_u64_s32 (int32x2_t) @end itemize @itemize @bullet -@item int64x1_t vreinterpret_s64_u8 (uint8x8_t) +@item uint64x1_t vreinterpret_u64_u8 (uint8x8_t) @end itemize @itemize @bullet -@item int64x1_t vreinterpret_s64_s32 (int32x2_t) +@item uint64x1_t vreinterpret_u64_u16 (uint16x4_t) @end itemize @itemize @bullet -@item int64x1_t vreinterpret_s64_s16 (int16x4_t) +@item uint64x1_t vreinterpret_u64_u32 (uint32x2_t) @end itemize @itemize @bullet -@item int64x1_t vreinterpret_s64_s8 (int8x8_t) +@item int8x8_t vreinterpret_s8_p8 (poly8x8_t) @end itemize @itemize @bullet -@item int64x1_t vreinterpret_s64_u64 (uint64x1_t) +@item int8x8_t vreinterpret_s8_p16 (poly16x4_t) @end itemize @itemize @bullet -@item int64x1_t vreinterpret_s64_f32 (float32x2_t) +@item int8x8_t vreinterpret_s8_f32 (float32x2_t) @end itemize @itemize @bullet -@item int64x1_t vreinterpret_s64_p16 (poly16x4_t) +@item int8x8_t vreinterpret_s8_p64 (poly64x1_t) @end itemize @itemize @bullet -@item int64x1_t vreinterpret_s64_p8 (poly8x8_t) +@item int8x8_t vreinterpret_s8_s64 (int64x1_t) @end itemize @itemize @bullet -@item int64x2_t vreinterpretq_s64_u32 (uint32x4_t) +@item int8x8_t vreinterpret_s8_u64 (uint64x1_t) @end itemize @itemize @bullet -@item int64x2_t vreinterpretq_s64_u16 (uint16x8_t) +@item int8x8_t vreinterpret_s8_s16 (int16x4_t) @end itemize @itemize @bullet -@item int64x2_t vreinterpretq_s64_u8 (uint8x16_t) +@item int8x8_t vreinterpret_s8_s32 (int32x2_t) @end itemize @itemize @bullet -@item int64x2_t vreinterpretq_s64_s32 (int32x4_t) +@item int8x8_t vreinterpret_s8_u8 (uint8x8_t) @end itemize @itemize @bullet -@item int64x2_t vreinterpretq_s64_s16 (int16x8_t) +@item int8x8_t vreinterpret_s8_u16 (uint16x4_t) @end itemize @itemize @bullet -@item int64x2_t vreinterpretq_s64_s8 (int8x16_t) +@item int8x8_t vreinterpret_s8_u32 (uint32x2_t) @end itemize @itemize @bullet -@item int64x2_t vreinterpretq_s64_u64 (uint64x2_t) +@item int16x4_t vreinterpret_s16_p8 (poly8x8_t) @end itemize @itemize @bullet -@item int64x2_t vreinterpretq_s64_f32 (float32x4_t) +@item int16x4_t vreinterpret_s16_p16 (poly16x4_t) @end itemize @itemize @bullet -@item int64x2_t vreinterpretq_s64_p16 (poly16x8_t) +@item int16x4_t vreinterpret_s16_f32 (float32x2_t) @end itemize @itemize @bullet -@item int64x2_t vreinterpretq_s64_p8 (poly8x16_t) +@item int16x4_t vreinterpret_s16_p64 (poly64x1_t) @end itemize @itemize @bullet -@item uint64x1_t vreinterpret_u64_u32 (uint32x2_t) +@item int16x4_t vreinterpret_s16_s64 (int64x1_t) @end itemize @itemize @bullet -@item uint64x1_t vreinterpret_u64_u16 (uint16x4_t) +@item int16x4_t vreinterpret_s16_u64 (uint64x1_t) @end itemize @itemize @bullet -@item uint64x1_t vreinterpret_u64_u8 (uint8x8_t) +@item int16x4_t vreinterpret_s16_s8 (int8x8_t) @end itemize @itemize @bullet -@item uint64x1_t vreinterpret_u64_s32 (int32x2_t) +@item int16x4_t vreinterpret_s16_s32 (int32x2_t) @end itemize @itemize @bullet -@item uint64x1_t vreinterpret_u64_s16 (int16x4_t) +@item int16x4_t vreinterpret_s16_u8 (uint8x8_t) @end itemize @itemize @bullet -@item uint64x1_t vreinterpret_u64_s8 (int8x8_t) +@item int16x4_t vreinterpret_s16_u16 (uint16x4_t) @end itemize @itemize @bullet -@item uint64x1_t vreinterpret_u64_s64 (int64x1_t) +@item int16x4_t vreinterpret_s16_u32 (uint32x2_t) @end itemize @itemize @bullet -@item uint64x1_t vreinterpret_u64_f32 (float32x2_t) +@item int32x2_t vreinterpret_s32_p8 (poly8x8_t) @end itemize @itemize @bullet -@item uint64x1_t vreinterpret_u64_p16 (poly16x4_t) +@item int32x2_t vreinterpret_s32_p16 (poly16x4_t) @end itemize @itemize @bullet -@item uint64x1_t vreinterpret_u64_p8 (poly8x8_t) +@item int32x2_t vreinterpret_s32_f32 (float32x2_t) @end itemize @itemize @bullet -@item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t) +@item int32x2_t vreinterpret_s32_p64 (poly64x1_t) @end itemize @itemize @bullet -@item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t) +@item int32x2_t vreinterpret_s32_s64 (int64x1_t) @end itemize @itemize @bullet -@item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t) +@item int32x2_t vreinterpret_s32_u64 (uint64x1_t) @end itemize @itemize @bullet -@item uint64x2_t vreinterpretq_u64_s32 (int32x4_t) +@item int32x2_t vreinterpret_s32_s8 (int8x8_t) @end itemize @itemize @bullet -@item uint64x2_t vreinterpretq_u64_s16 (int16x8_t) +@item int32x2_t vreinterpret_s32_s16 (int16x4_t) @end itemize @itemize @bullet -@item uint64x2_t vreinterpretq_u64_s8 (int8x16_t) +@item int32x2_t vreinterpret_s32_u8 (uint8x8_t) @end itemize @itemize @bullet -@item uint64x2_t vreinterpretq_u64_s64 (int64x2_t) +@item int32x2_t vreinterpret_s32_u16 (uint16x4_t) @end itemize @itemize @bullet -@item uint64x2_t vreinterpretq_u64_f32 (float32x4_t) +@item int32x2_t vreinterpret_s32_u32 (uint32x2_t) @end itemize @itemize @bullet -@item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t) +@item uint8x8_t vreinterpret_u8_p8 (poly8x8_t) @end itemize @itemize @bullet -@item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t) +@item uint8x8_t vreinterpret_u8_p16 (poly16x4_t) @end itemize @itemize @bullet -@item int8x8_t vreinterpret_s8_u32 (uint32x2_t) +@item uint8x8_t vreinterpret_u8_f32 (float32x2_t) @end itemize @itemize @bullet -@item int8x8_t vreinterpret_s8_u16 (uint16x4_t) +@item uint8x8_t vreinterpret_u8_p64 (poly64x1_t) @end itemize @itemize @bullet -@item int8x8_t vreinterpret_s8_u8 (uint8x8_t) +@item uint8x8_t vreinterpret_u8_s64 (int64x1_t) @end itemize @itemize @bullet -@item int8x8_t vreinterpret_s8_s32 (int32x2_t) +@item uint8x8_t vreinterpret_u8_u64 (uint64x1_t) @end itemize @itemize @bullet -@item int8x8_t vreinterpret_s8_s16 (int16x4_t) +@item uint8x8_t vreinterpret_u8_s8 (int8x8_t) @end itemize @itemize @bullet -@item int8x8_t vreinterpret_s8_u64 (uint64x1_t) +@item uint8x8_t vreinterpret_u8_s16 (int16x4_t) @end itemize @itemize @bullet -@item int8x8_t vreinterpret_s8_s64 (int64x1_t) +@item uint8x8_t vreinterpret_u8_s32 (int32x2_t) @end itemize @itemize @bullet -@item int8x8_t vreinterpret_s8_f32 (float32x2_t) +@item uint8x8_t vreinterpret_u8_u16 (uint16x4_t) @end itemize @itemize @bullet -@item int8x8_t vreinterpret_s8_p16 (poly16x4_t) +@item uint8x8_t vreinterpret_u8_u32 (uint32x2_t) @end itemize @itemize @bullet -@item int8x8_t vreinterpret_s8_p8 (poly8x8_t) +@item uint16x4_t vreinterpret_u16_p8 (poly8x8_t) @end itemize @itemize @bullet -@item int8x16_t vreinterpretq_s8_u32 (uint32x4_t) +@item uint16x4_t vreinterpret_u16_p16 (poly16x4_t) @end itemize @itemize @bullet -@item int8x16_t vreinterpretq_s8_u16 (uint16x8_t) +@item uint16x4_t vreinterpret_u16_f32 (float32x2_t) @end itemize @itemize @bullet -@item int8x16_t vreinterpretq_s8_u8 (uint8x16_t) +@item uint16x4_t vreinterpret_u16_p64 (poly64x1_t) @end itemize @itemize @bullet -@item int8x16_t vreinterpretq_s8_s32 (int32x4_t) +@item uint16x4_t vreinterpret_u16_s64 (int64x1_t) @end itemize @itemize @bullet -@item int8x16_t vreinterpretq_s8_s16 (int16x8_t) +@item uint16x4_t vreinterpret_u16_u64 (uint64x1_t) @end itemize @itemize @bullet -@item int8x16_t vreinterpretq_s8_u64 (uint64x2_t) +@item uint16x4_t vreinterpret_u16_s8 (int8x8_t) @end itemize @itemize @bullet -@item int8x16_t vreinterpretq_s8_s64 (int64x2_t) +@item uint16x4_t vreinterpret_u16_s16 (int16x4_t) @end itemize @itemize @bullet -@item int8x16_t vreinterpretq_s8_f32 (float32x4_t) +@item uint16x4_t vreinterpret_u16_s32 (int32x2_t) @end itemize @itemize @bullet -@item int8x16_t vreinterpretq_s8_p16 (poly16x8_t) +@item uint16x4_t vreinterpret_u16_u8 (uint8x8_t) @end itemize @itemize @bullet -@item int8x16_t vreinterpretq_s8_p8 (poly8x16_t) +@item uint16x4_t vreinterpret_u16_u32 (uint32x2_t) @end itemize @itemize @bullet -@item int16x4_t vreinterpret_s16_u32 (uint32x2_t) +@item uint32x2_t vreinterpret_u32_p8 (poly8x8_t) @end itemize @itemize @bullet -@item int16x4_t vreinterpret_s16_u16 (uint16x4_t) +@item uint32x2_t vreinterpret_u32_p16 (poly16x4_t) @end itemize @itemize @bullet -@item int16x4_t vreinterpret_s16_u8 (uint8x8_t) +@item uint32x2_t vreinterpret_u32_f32 (float32x2_t) @end itemize @itemize @bullet -@item int16x4_t vreinterpret_s16_s32 (int32x2_t) +@item uint32x2_t vreinterpret_u32_p64 (poly64x1_t) @end itemize @itemize @bullet -@item int16x4_t vreinterpret_s16_s8 (int8x8_t) +@item uint32x2_t vreinterpret_u32_s64 (int64x1_t) @end itemize @itemize @bullet -@item int16x4_t vreinterpret_s16_u64 (uint64x1_t) +@item uint32x2_t vreinterpret_u32_u64 (uint64x1_t) @end itemize @itemize @bullet -@item int16x4_t vreinterpret_s16_s64 (int64x1_t) +@item uint32x2_t vreinterpret_u32_s8 (int8x8_t) @end itemize @itemize @bullet -@item int16x4_t vreinterpret_s16_f32 (float32x2_t) +@item uint32x2_t vreinterpret_u32_s16 (int16x4_t) @end itemize @itemize @bullet -@item int16x4_t vreinterpret_s16_p16 (poly16x4_t) +@item uint32x2_t vreinterpret_u32_s32 (int32x2_t) @end itemize @itemize @bullet -@item int16x4_t vreinterpret_s16_p8 (poly8x8_t) +@item uint32x2_t vreinterpret_u32_u8 (uint8x8_t) @end itemize @itemize @bullet -@item int16x8_t vreinterpretq_s16_u32 (uint32x4_t) +@item uint32x2_t vreinterpret_u32_u16 (uint16x4_t) @end itemize @itemize @bullet -@item int16x8_t vreinterpretq_s16_u16 (uint16x8_t) +@item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t) @end itemize @itemize @bullet -@item int16x8_t vreinterpretq_s16_u8 (uint8x16_t) +@item poly8x16_t vreinterpretq_p8_f32 (float32x4_t) @end itemize @itemize @bullet -@item int16x8_t vreinterpretq_s16_s32 (int32x4_t) +@item poly8x16_t vreinterpretq_p8_p64 (poly64x2_t) @end itemize @itemize @bullet -@item int16x8_t vreinterpretq_s16_s8 (int8x16_t) +@item poly8x16_t vreinterpretq_p8_p128 (poly128_t) @end itemize @itemize @bullet -@item int16x8_t vreinterpretq_s16_u64 (uint64x2_t) +@item poly8x16_t vreinterpretq_p8_s64 (int64x2_t) @end itemize @itemize @bullet -@item int16x8_t vreinterpretq_s16_s64 (int64x2_t) +@item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t) @end itemize @itemize @bullet -@item int16x8_t vreinterpretq_s16_f32 (float32x4_t) +@item poly8x16_t vreinterpretq_p8_s8 (int8x16_t) @end itemize @itemize @bullet -@item int16x8_t vreinterpretq_s16_p16 (poly16x8_t) +@item poly8x16_t vreinterpretq_p8_s16 (int16x8_t) @end itemize @itemize @bullet -@item int16x8_t vreinterpretq_s16_p8 (poly8x16_t) +@item poly8x16_t vreinterpretq_p8_s32 (int32x4_t) @end itemize @itemize @bullet -@item int32x2_t vreinterpret_s32_u32 (uint32x2_t) +@item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t) @end itemize @itemize @bullet -@item int32x2_t vreinterpret_s32_u16 (uint16x4_t) +@item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t) @end itemize @itemize @bullet -@item int32x2_t vreinterpret_s32_u8 (uint8x8_t) +@item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t) @end itemize @itemize @bullet -@item int32x2_t vreinterpret_s32_s16 (int16x4_t) +@item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t) @end itemize @itemize @bullet -@item int32x2_t vreinterpret_s32_s8 (int8x8_t) +@item poly16x8_t vreinterpretq_p16_f32 (float32x4_t) @end itemize @itemize @bullet -@item int32x2_t vreinterpret_s32_u64 (uint64x1_t) +@item poly16x8_t vreinterpretq_p16_p64 (poly64x2_t) @end itemize @itemize @bullet -@item int32x2_t vreinterpret_s32_s64 (int64x1_t) +@item poly16x8_t vreinterpretq_p16_p128 (poly128_t) @end itemize @itemize @bullet -@item int32x2_t vreinterpret_s32_f32 (float32x2_t) +@item poly16x8_t vreinterpretq_p16_s64 (int64x2_t) @end itemize @itemize @bullet -@item int32x2_t vreinterpret_s32_p16 (poly16x4_t) +@item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t) @end itemize @itemize @bullet -@item int32x2_t vreinterpret_s32_p8 (poly8x8_t) +@item poly16x8_t vreinterpretq_p16_s8 (int8x16_t) @end itemize @itemize @bullet -@item int32x4_t vreinterpretq_s32_u32 (uint32x4_t) +@item poly16x8_t vreinterpretq_p16_s16 (int16x8_t) @end itemize @itemize @bullet -@item int32x4_t vreinterpretq_s32_u16 (uint16x8_t) +@item poly16x8_t vreinterpretq_p16_s32 (int32x4_t) @end itemize @itemize @bullet -@item int32x4_t vreinterpretq_s32_u8 (uint8x16_t) +@item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t) @end itemize @itemize @bullet -@item int32x4_t vreinterpretq_s32_s16 (int16x8_t) +@item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t) @end itemize @itemize @bullet -@item int32x4_t vreinterpretq_s32_s8 (int8x16_t) +@item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t) @end itemize @itemize @bullet -@item int32x4_t vreinterpretq_s32_u64 (uint64x2_t) +@item float32x4_t vreinterpretq_f32_p8 (poly8x16_t) @end itemize @itemize @bullet -@item int32x4_t vreinterpretq_s32_s64 (int64x2_t) +@item float32x4_t vreinterpretq_f32_p16 (poly16x8_t) @end itemize @itemize @bullet -@item int32x4_t vreinterpretq_s32_f32 (float32x4_t) +@item float32x4_t vreinterpretq_f32_p64 (poly64x2_t) @end itemize @itemize @bullet -@item int32x4_t vreinterpretq_s32_p16 (poly16x8_t) +@item float32x4_t vreinterpretq_f32_p128 (poly128_t) @end itemize @itemize @bullet -@item int32x4_t vreinterpretq_s32_p8 (poly8x16_t) +@item float32x4_t vreinterpretq_f32_s64 (int64x2_t) @end itemize @itemize @bullet -@item uint8x8_t vreinterpret_u8_u32 (uint32x2_t) +@item float32x4_t vreinterpretq_f32_u64 (uint64x2_t) @end itemize @itemize @bullet -@item uint8x8_t vreinterpret_u8_u16 (uint16x4_t) +@item float32x4_t vreinterpretq_f32_s8 (int8x16_t) @end itemize @itemize @bullet -@item uint8x8_t vreinterpret_u8_s32 (int32x2_t) +@item float32x4_t vreinterpretq_f32_s16 (int16x8_t) @end itemize @itemize @bullet -@item uint8x8_t vreinterpret_u8_s16 (int16x4_t) +@item float32x4_t vreinterpretq_f32_s32 (int32x4_t) @end itemize @itemize @bullet -@item uint8x8_t vreinterpret_u8_s8 (int8x8_t) +@item float32x4_t vreinterpretq_f32_u8 (uint8x16_t) @end itemize @itemize @bullet -@item uint8x8_t vreinterpret_u8_u64 (uint64x1_t) +@item float32x4_t vreinterpretq_f32_u16 (uint16x8_t) @end itemize @itemize @bullet -@item uint8x8_t vreinterpret_u8_s64 (int64x1_t) +@item float32x4_t vreinterpretq_f32_u32 (uint32x4_t) @end itemize @itemize @bullet -@item uint8x8_t vreinterpret_u8_f32 (float32x2_t) +@item poly64x2_t vreinterpretq_p64_p8 (poly8x16_t) @end itemize @itemize @bullet -@item uint8x8_t vreinterpret_u8_p16 (poly16x4_t) +@item poly64x2_t vreinterpretq_p64_p16 (poly16x8_t) @end itemize @itemize @bullet -@item uint8x8_t vreinterpret_u8_p8 (poly8x8_t) +@item poly64x2_t vreinterpretq_p64_f32 (float32x4_t) @end itemize @itemize @bullet -@item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t) +@item poly64x2_t vreinterpretq_p64_p128 (poly128_t) @end itemize @itemize @bullet -@item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t) +@item poly64x2_t vreinterpretq_p64_s64 (int64x2_t) @end itemize @itemize @bullet -@item uint8x16_t vreinterpretq_u8_s32 (int32x4_t) +@item poly64x2_t vreinterpretq_p64_u64 (uint64x2_t) @end itemize @itemize @bullet -@item uint8x16_t vreinterpretq_u8_s16 (int16x8_t) +@item poly64x2_t vreinterpretq_p64_s8 (int8x16_t) @end itemize @itemize @bullet -@item uint8x16_t vreinterpretq_u8_s8 (int8x16_t) +@item poly64x2_t vreinterpretq_p64_s16 (int16x8_t) @end itemize @itemize @bullet -@item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t) +@item poly64x2_t vreinterpretq_p64_s32 (int32x4_t) @end itemize @itemize @bullet -@item uint8x16_t vreinterpretq_u8_s64 (int64x2_t) +@item poly64x2_t vreinterpretq_p64_u8 (uint8x16_t) @end itemize @itemize @bullet -@item uint8x16_t vreinterpretq_u8_f32 (float32x4_t) +@item poly64x2_t vreinterpretq_p64_u16 (uint16x8_t) @end itemize @itemize @bullet -@item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t) +@item poly64x2_t vreinterpretq_p64_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_p64 (poly64x2_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item poly128_t vreinterpretq_p128_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_p64 (poly64x2_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_p128 (poly128_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item int64x2_t vreinterpretq_s64_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_p64 (poly64x2_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_p128 (poly128_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_p64 (poly64x2_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_p128 (poly128_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item int8x16_t vreinterpretq_s8_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_p64 (poly64x2_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_p128 (poly128_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_s32 (int32x4_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item int16x8_t vreinterpretq_s16_u32 (uint32x4_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_p8 (poly8x16_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_p16 (poly16x8_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_f32 (float32x4_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_p64 (poly64x2_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_p128 (poly128_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_s64 (int64x2_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_u64 (uint64x2_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_s8 (int8x16_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_s16 (int16x8_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_u8 (uint8x16_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_u16 (uint16x8_t) +@end itemize + + +@itemize @bullet +@item int32x4_t vreinterpretq_s32_u32 (uint32x4_t) @end itemize @@ -11186,82 +11753,82 @@ @itemize @bullet -@item uint16x4_t vreinterpret_u16_u32 (uint32x2_t) +@item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t) @end itemize @itemize @bullet -@item uint16x4_t vreinterpret_u16_u8 (uint8x8_t) +@item uint8x16_t vreinterpretq_u8_f32 (float32x4_t) @end itemize @itemize @bullet -@item uint16x4_t vreinterpret_u16_s32 (int32x2_t) +@item uint8x16_t vreinterpretq_u8_p64 (poly64x2_t) @end itemize @itemize @bullet -@item uint16x4_t vreinterpret_u16_s16 (int16x4_t) +@item uint8x16_t vreinterpretq_u8_p128 (poly128_t) @end itemize @itemize @bullet -@item uint16x4_t vreinterpret_u16_s8 (int8x8_t) +@item uint8x16_t vreinterpretq_u8_s64 (int64x2_t) @end itemize @itemize @bullet -@item uint16x4_t vreinterpret_u16_u64 (uint64x1_t) +@item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t) @end itemize @itemize @bullet -@item uint16x4_t vreinterpret_u16_s64 (int64x1_t) +@item uint8x16_t vreinterpretq_u8_s8 (int8x16_t) @end itemize @itemize @bullet -@item uint16x4_t vreinterpret_u16_f32 (float32x2_t) +@item uint8x16_t vreinterpretq_u8_s16 (int16x8_t) @end itemize @itemize @bullet -@item uint16x4_t vreinterpret_u16_p16 (poly16x4_t) +@item uint8x16_t vreinterpretq_u8_s32 (int32x4_t) @end itemize @itemize @bullet -@item uint16x4_t vreinterpret_u16_p8 (poly8x8_t) +@item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t) @end itemize @itemize @bullet -@item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t) +@item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t) @end itemize @itemize @bullet -@item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t) +@item uint16x8_t vreinterpretq_u16_p8 (poly8x16_t) @end itemize @itemize @bullet -@item uint16x8_t vreinterpretq_u16_s32 (int32x4_t) +@item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t) @end itemize @itemize @bullet -@item uint16x8_t vreinterpretq_u16_s16 (int16x8_t) +@item uint16x8_t vreinterpretq_u16_f32 (float32x4_t) @end itemize @itemize @bullet -@item uint16x8_t vreinterpretq_u16_s8 (int8x16_t) +@item uint16x8_t vreinterpretq_u16_p64 (poly64x2_t) @end itemize @itemize @bullet -@item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t) +@item uint16x8_t vreinterpretq_u16_p128 (poly128_t) @end itemize @@ -11271,77 +11838,77 @@ @itemize @bullet -@item uint16x8_t vreinterpretq_u16_f32 (float32x4_t) +@item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t) @end itemize @itemize @bullet -@item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t) +@item uint16x8_t vreinterpretq_u16_s8 (int8x16_t) @end itemize @itemize @bullet -@item uint16x8_t vreinterpretq_u16_p8 (poly8x16_t) +@item uint16x8_t vreinterpretq_u16_s16 (int16x8_t) @end itemize @itemize @bullet -@item uint32x2_t vreinterpret_u32_u16 (uint16x4_t) +@item uint16x8_t vreinterpretq_u16_s32 (int32x4_t) @end itemize @itemize @bullet -@item uint32x2_t vreinterpret_u32_u8 (uint8x8_t) +@item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t) @end itemize @itemize @bullet -@item uint32x2_t vreinterpret_u32_s32 (int32x2_t) +@item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t) @end itemize @itemize @bullet -@item uint32x2_t vreinterpret_u32_s16 (int16x4_t) +@item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t) @end itemize @itemize @bullet -@item uint32x2_t vreinterpret_u32_s8 (int8x8_t) +@item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t) @end itemize @itemize @bullet -@item uint32x2_t vreinterpret_u32_u64 (uint64x1_t) +@item uint32x4_t vreinterpretq_u32_f32 (float32x4_t) @end itemize @itemize @bullet -@item uint32x2_t vreinterpret_u32_s64 (int64x1_t) +@item uint32x4_t vreinterpretq_u32_p64 (poly64x2_t) @end itemize @itemize @bullet -@item uint32x2_t vreinterpret_u32_f32 (float32x2_t) +@item uint32x4_t vreinterpretq_u32_p128 (poly128_t) @end itemize @itemize @bullet -@item uint32x2_t vreinterpret_u32_p16 (poly16x4_t) +@item uint32x4_t vreinterpretq_u32_s64 (int64x2_t) @end itemize @itemize @bullet -@item uint32x2_t vreinterpret_u32_p8 (poly8x8_t) +@item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t) @end itemize @itemize @bullet -@item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t) +@item uint32x4_t vreinterpretq_u32_s8 (int8x16_t) @end itemize @itemize @bullet -@item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t) +@item uint32x4_t vreinterpretq_u32_s16 (int16x8_t) @end itemize @@ -11351,39 +11918,91 @@ @itemize @bullet -@item uint32x4_t vreinterpretq_u32_s16 (int16x8_t) +@item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t) @end itemize @itemize @bullet -@item uint32x4_t vreinterpretq_u32_s8 (int8x16_t) +@item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t) @end itemize + + + @itemize @bullet -@item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t) +@item poly128_t vldrq_p128(poly128_t const *) @end itemize +@itemize @bullet +@item void vstrq_p128(poly128_t *, poly128_t) +@end itemize @itemize @bullet -@item uint32x4_t vreinterpretq_u32_s64 (int64x2_t) +@item uint64x1_t vceq_p64 (poly64x1_t, poly64x1_t) @end itemize +@itemize @bullet +@item uint64x1_t vtst_p64 (poly64x1_t, poly64x1_t) +@end itemize @itemize @bullet -@item uint32x4_t vreinterpretq_u32_f32 (float32x4_t) +@item uint32_t vsha1h_u32 (uint32_t) +@*@emph{Form of expected instruction(s):} @code{sha1h.32 @var{q0}, @var{q1}} @end itemize +@itemize @bullet +@item uint32x4_t vsha1cq_u32 (uint32x4_t, uint32_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{sha1c.32 @var{q0}, @var{q1}, @var{q2}} +@end itemize @itemize @bullet -@item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t) +@item uint32x4_t vsha1pq_u32 (uint32x4_t, uint32_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{sha1p.32 @var{q0}, @var{q1}, @var{q2}} @end itemize +@itemize @bullet +@item uint32x4_t vsha1mq_u32 (uint32x4_t, uint32_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{sha1m.32 @var{q0}, @var{q1}, @var{q2}} +@end itemize @itemize @bullet -@item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t) +@item uint32x4_t vsha1su0q_u32 (uint32x4_t, uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{sha1su0.32 @var{q0}, @var{q1}, @var{q2}} +@end itemize + +@itemize @bullet +@item uint32x4_t vsha1su1q_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{sha1su1.32 @var{q0}, @var{q1}, @var{q2}} @end itemize +@itemize @bullet +@item uint32x4_t vsha256hq_u32 (uint32x4_t, uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{sha256h.32 @var{q0}, @var{q1}, @var{q2}} +@end itemize + +@itemize @bullet +@item uint32x4_t vsha256h2q_u32 (uint32x4_t, uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{sha256h2.32 @var{q0}, @var{q1}, @var{q2}} +@end itemize + +@itemize @bullet +@item uint32x4_t vsha256su0q_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{sha256su0.32 @var{q0}, @var{q1}} +@end itemize + +@itemize @bullet +@item uint32x4_t vsha256su1q_u32 (uint32x4_t, uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{sha256su1.32 @var{q0}, @var{q1}, @var{q2}} +@end itemize +@itemize @bullet +@item poly128_t vmull_p64 (poly64_t a, poly64_t b) +@*@emph{Form of expected instruction(s):} @code{vmull.p64 @var{q0}, @var{d1}, @var{d2}} +@end itemize +@itemize @bullet +@item poly128_t vmull_high_p64 (poly64x2_t a, poly64x2_t b) +@*@emph{Form of expected instruction(s):} @code{vmull.p64 @var{q0}, @var{d1}, @var{d2}} +@end itemize diff --git a/gcc/doc/avr-mmcu.texi b/gcc/doc/avr-mmcu.texi index 838394d2bab..cd167c5e389 100644 --- a/gcc/doc/avr-mmcu.texi +++ b/gcc/doc/avr-mmcu.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2012-2013 Free Software Foundation, Inc. +@c Copyright (C) 2012-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc/doc/include/fdl.texi. diff --git a/gcc/doc/bugreport.texi b/gcc/doc/bugreport.texi index f728f176bbb..be035222597 100644 --- a/gcc/doc/bugreport.texi +++ b/gcc/doc/bugreport.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/cfg.texi b/gcc/doc/cfg.texi index b759e36ff75..63b8dd58614 100644 --- a/gcc/doc/cfg.texi +++ b/gcc/doc/cfg.texi @@ -1,5 +1,5 @@ @c -*-texinfo-*- -@c Copyright (C) 2001-2013 Free Software Foundation, Inc. +@c Copyright (C) 2001-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -23,7 +23,7 @@ used to represent the control flow graph are defined in In GCC, the representation of control flow is maintained throughout the compilation process, from constructing the CFG early in -@code{pass_build_cfg} to @code{pass_free_cfg} (see @file{passes.c}). +@code{pass_build_cfg} to @code{pass_free_cfg} (see @file{passes.def}). The CFG takes various different modes and may undergo extensive manipulations, but the graph is always valid between its construction and its release. This way, transfer of information such as data flow, diff --git a/gcc/doc/collect2.texi b/gcc/doc/collect2.texi index 4cc4ae38d53..d56c7a4f47e 100644 --- a/gcc/doc/collect2.texi +++ b/gcc/doc/collect2.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/compat.texi b/gcc/doc/compat.texi index 1bf97130b1f..c42c38de825 100644 --- a/gcc/doc/compat.texi +++ b/gcc/doc/compat.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2002-2013 Free Software Foundation, Inc. +@c Copyright (C) 2002-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/configfiles.texi b/gcc/doc/configfiles.texi index be58eca8934..5811b8fa92a 100644 --- a/gcc/doc/configfiles.texi +++ b/gcc/doc/configfiles.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/configterms.texi b/gcc/doc/configterms.texi index 383ef78a998..776b4bb8b45 100644 --- a/gcc/doc/configterms.texi +++ b/gcc/doc/configterms.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2001-2013 Free Software Foundation, Inc. +@c Copyright (C) 2001-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi index 32a85634eb8..fb856950327 100644 --- a/gcc/doc/contrib.texi +++ b/gcc/doc/contrib.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/contribute.texi b/gcc/doc/contribute.texi index 9b3ebce3791..88cc72a10d3 100644 --- a/gcc/doc/contribute.texi +++ b/gcc/doc/contribute.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/cpp.texi b/gcc/doc/cpp.texi index 0ab9361bb42..aaed739fb35 100644 --- a/gcc/doc/cpp.texi +++ b/gcc/doc/cpp.texi @@ -10,7 +10,7 @@ @copying @c man begin COPYRIGHT -Copyright @copyright{} 1987-2013 Free Software Foundation, Inc. +Copyright @copyright{} 1987-2014 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or diff --git a/gcc/doc/cppenv.texi b/gcc/doc/cppenv.texi index adf2d0f194b..2116ccefd3e 100644 --- a/gcc/doc/cppenv.texi +++ b/gcc/doc/cppenv.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1999-2013 Free Software Foundation, Inc. +@c Copyright (C) 1999-2014 Free Software Foundation, Inc. @c This is part of the CPP and GCC manuals. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/cppinternals.texi b/gcc/doc/cppinternals.texi index f78c4d3b2ea..8b329d6c173 100644 --- a/gcc/doc/cppinternals.texi +++ b/gcc/doc/cppinternals.texi @@ -18,7 +18,7 @@ @ifinfo This file documents the internals of the GNU C Preprocessor. -Copyright (C) 2000-2013 Free Software Foundation, Inc. +Copyright (C) 2000-2014 Free Software Foundation, Inc. Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice @@ -47,7 +47,7 @@ into another language, under the above conditions for modified versions. @page @vskip 0pt plus 1filll @c man begin COPYRIGHT -Copyright @copyright{} 2000-2013 Free Software Foundation, Inc. +Copyright @copyright{} 2000-2014 Free Software Foundation, Inc. Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice diff --git a/gcc/doc/cppopts.texi b/gcc/doc/cppopts.texi index 67b5c7873b9..b2127e4684c 100644 --- a/gcc/doc/cppopts.texi +++ b/gcc/doc/cppopts.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1999-2013 Free Software Foundation, Inc. +@c Copyright (C) 1999-2014 Free Software Foundation, Inc. @c This is part of the CPP and GCC manuals. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index af258d72faf..84fd594b605 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -3266,6 +3266,17 @@ this function attribute to make GCC generate the ``hot-patching'' function prologue used in Win32 API functions in Microsoft Windows XP Service Pack 2 and newer. +@item hotpatch [(@var{prologue-halfwords})] +@cindex @code{hotpatch} attribute + +On S/390 System z targets, you can use this function attribute to +make GCC generate a ``hot-patching'' function prologue. The +@code{hotpatch} has no effect on funtions that are explicitly +inline. If the @option{-mhotpatch} or @option{-mno-hotpatch} +command-line option is used at the same time, the @code{hotpatch} +attribute takes precedence. If an argument is given, the maximum +allowed value is 1000000. + @item naked @cindex function without a prologue/epilogue code Use this attribute on the ARM, AVR, MCORE, MSP430, NDS32, RL78, RX and SPU @@ -3836,6 +3847,14 @@ int core2_func (void) __attribute__ ((__target__ ("arch=core2"))); int sse3_func (void) __attribute__ ((__target__ ("sse3"))); @end smallexample +You can either use multiple +strings to specify multiple options, or separate the options +with a comma (@samp{,}). + +The @code{target} attribute is presently implemented for +i386/x86_64, PowerPC, and Nios II targets only. +The options supported are specific to each target. + On the 386, the following options are allowed: @table @samp @@ -4157,9 +4176,29 @@ compilation tunes for the @var{CPU} architecture, and not the default tuning specified on the command line. @end table -On the 386/x86_64 and PowerPC back ends, you can use either multiple -strings to specify multiple options, or you can separate the option -with a comma (@code{,}). +When compiling for Nios II, the following options are allowed: + +@table @samp +@item custom-@var{insn}=@var{N} +@itemx no-custom-@var{insn} +@cindex @code{target("custom-@var{insn}=@var{N}")} attribute +@cindex @code{target("no-custom-@var{insn}")} attribute +Each @samp{custom-@var{insn}=@var{N}} attribute locally enables use of a +custom instruction with encoding @var{N} when generating code that uses +@var{insn}. Similarly, @samp{no-custom-@var{insn}} locally inhibits use of +the custom instruction @var{insn}. +These target attributes correspond to the +@option{-mcustom-@var{insn}=@var{N}} and @option{-mno-custom-@var{insn}} +command-line options, and support the same set of @var{insn} keywords. +@xref{Nios II Options}, for more information. + +@item custom-fpu-cfg=@var{name} +@cindex @code{target("custom-fpu-cfg=@var{name}")} attribute +This attribute corresponds to the @option{-mcustom-fpu-cfg=@var{name}} +command-line option, to select a predefined set of custom instructions +named @var{name}. +@xref{Nios II Options}, for more information. +@end table On the 386/x86_64 and PowerPC back ends, the inliner does not inline a function that has different target options than the caller, unless the @@ -4167,10 +4206,6 @@ callee has a subset of the target options of the caller. For example a function declared with @code{target("sse3")} can inline a function with @code{target("sse2")}, since @code{-msse3} implies @code{-msse2}. -The @code{target} attribute is not implemented in GCC versions earlier -than 4.4 for the i386/x86_64 and 4.6 for the PowerPC back ends. It is -not currently implemented for other back ends. - @item tiny_data @cindex tiny data section on the H8/300H and H8S Use this attribute on the H8/300H and H8S to indicate that the specified @@ -8693,12 +8728,12 @@ This function is the equivalent to the preprocessor @code{__LINE__} macro and returns the line number of the invocation of the built-in. @end deftypefn -@deftypefn {Built-in Function} int __builtin_FUNCTION () +@deftypefn {Built-in Function} {const char *} __builtin_FUNCTION () This function is the equivalent to the preprocessor @code{__FUNCTION__} macro and returns the function name the invocation of the built-in is in. @end deftypefn -@deftypefn {Built-in Function} int __builtin_FILE () +@deftypefn {Built-in Function} {const char *} __builtin_FILE () This function is the equivalent to the preprocessor @code{__FILE__} macro and returns the file name the invocation of the built-in is in. @end deftypefn @@ -9001,10 +9036,12 @@ instructions, but allow the compiler to schedule those calls. @menu * Alpha Built-in Functions:: +* Altera Nios II Built-in Functions:: * ARC Built-in Functions:: * ARC SIMD Built-in Functions:: * ARM iWMMXt Built-in Functions:: * ARM NEON Intrinsics:: +* ARM ACLE Intrinsics:: * AVR Built-in Functions:: * Blackfin Built-in Functions:: * FR-V Built-in Functions:: @@ -9112,6 +9149,110 @@ void *__builtin_thread_pointer (void) void __builtin_set_thread_pointer (void *) @end smallexample +@node Altera Nios II Built-in Functions +@subsection Altera Nios II Built-in Functions + +These built-in functions are available for the Altera Nios II +family of processors. + +The following built-in functions are always available. They +all generate the machine instruction that is part of the name. + +@example +int __builtin_ldbio (volatile const void *) +int __builtin_ldbuio (volatile const void *) +int __builtin_ldhio (volatile const void *) +int __builtin_ldhuio (volatile const void *) +int __builtin_ldwio (volatile const void *) +void __builtin_stbio (volatile void *, int) +void __builtin_sthio (volatile void *, int) +void __builtin_stwio (volatile void *, int) +void __builtin_sync (void) +int __builtin_rdctl (int) +void __builtin_wrctl (int, int) +@end example + +The following built-in functions are always available. They +all generate a Nios II Custom Instruction. The name of the +function represents the types that the function takes and +returns. The letter before the @code{n} is the return type +or void if absent. The @code{n} represents the first parameter +to all the custom instructions, the custom instruction number. +The two letters after the @code{n} represent the up to two +parameters to the function. + +The letters represent the following data types: +@table @code +@item <no letter> +@code{void} for return type and no parameter for parameter types. + +@item i +@code{int} for return type and parameter type + +@item f +@code{float} for return type and parameter type + +@item p +@code{void *} for return type and parameter type + +@end table + +And the function names are: +@example +void __builtin_custom_n (void) +void __builtin_custom_ni (int) +void __builtin_custom_nf (float) +void __builtin_custom_np (void *) +void __builtin_custom_nii (int, int) +void __builtin_custom_nif (int, float) +void __builtin_custom_nip (int, void *) +void __builtin_custom_nfi (float, int) +void __builtin_custom_nff (float, float) +void __builtin_custom_nfp (float, void *) +void __builtin_custom_npi (void *, int) +void __builtin_custom_npf (void *, float) +void __builtin_custom_npp (void *, void *) +int __builtin_custom_in (void) +int __builtin_custom_ini (int) +int __builtin_custom_inf (float) +int __builtin_custom_inp (void *) +int __builtin_custom_inii (int, int) +int __builtin_custom_inif (int, float) +int __builtin_custom_inip (int, void *) +int __builtin_custom_infi (float, int) +int __builtin_custom_inff (float, float) +int __builtin_custom_infp (float, void *) +int __builtin_custom_inpi (void *, int) +int __builtin_custom_inpf (void *, float) +int __builtin_custom_inpp (void *, void *) +float __builtin_custom_fn (void) +float __builtin_custom_fni (int) +float __builtin_custom_fnf (float) +float __builtin_custom_fnp (void *) +float __builtin_custom_fnii (int, int) +float __builtin_custom_fnif (int, float) +float __builtin_custom_fnip (int, void *) +float __builtin_custom_fnfi (float, int) +float __builtin_custom_fnff (float, float) +float __builtin_custom_fnfp (float, void *) +float __builtin_custom_fnpi (void *, int) +float __builtin_custom_fnpf (void *, float) +float __builtin_custom_fnpp (void *, void *) +void * __builtin_custom_pn (void) +void * __builtin_custom_pni (int) +void * __builtin_custom_pnf (float) +void * __builtin_custom_pnp (void *) +void * __builtin_custom_pnii (int, int) +void * __builtin_custom_pnif (int, float) +void * __builtin_custom_pnip (int, void *) +void * __builtin_custom_pnfi (float, int) +void * __builtin_custom_pnff (float, float) +void * __builtin_custom_pnfp (float, void *) +void * __builtin_custom_pnpi (void *, int) +void * __builtin_custom_pnpf (void *, float) +void * __builtin_custom_pnpp (void *, void *) +@end example + @node ARC Built-in Functions @subsection ARC Built-in Functions @@ -9697,6 +9838,14 @@ when the @option{-mfpu=neon} switch is used: @include arm-neon-intrinsics.texi +@node ARM ACLE Intrinsics +@subsection ARM ACLE Intrinsics + +These built-in intrinsics for the ARMv8-A CRC32 extension are available when +the @option{-march=armv8-a+crc} switch is used: + +@include arm-acle-intrinsics.texi + @node AVR Built-in Functions @subsection AVR Built-in Functions @@ -16270,9 +16419,8 @@ function. The parenthesis around the options is optional. @xref{Function Attributes}, for more information about the @code{target} attribute and the attribute syntax. -The @code{#pragma GCC target} attribute is not implemented in GCC versions earlier -than 4.4 for the i386/x86_64 and 4.6 for the PowerPC back ends. At -present, it is not implemented for other back ends. +The @code{#pragma GCC target} pragma is presently implemented for +i386/x86_64, PowerPC, and Nios II targets only. @end table @table @code diff --git a/gcc/doc/fragments.texi b/gcc/doc/fragments.texi index b9a0c34b690..2eff7f7dca6 100644 --- a/gcc/doc/fragments.texi +++ b/gcc/doc/fragments.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/frontends.texi b/gcc/doc/frontends.texi index 6208fdc8afb..cd8f3caadd7 100644 --- a/gcc/doc/frontends.texi +++ b/gcc/doc/frontends.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/gcc.texi b/gcc/doc/gcc.texi index 55307cd35ee..1e0fc46d00b 100644 --- a/gcc/doc/gcc.texi +++ b/gcc/doc/gcc.texi @@ -40,7 +40,7 @@ @c %**end of header @copying -Copyright @copyright{} 1988-2013 Free Software Foundation, Inc. +Copyright @copyright{} 1988-2014 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or diff --git a/gcc/doc/gccint.texi b/gcc/doc/gccint.texi index 7d795000c0e..889f410c563 100644 --- a/gcc/doc/gccint.texi +++ b/gcc/doc/gccint.texi @@ -26,7 +26,7 @@ @c %**end of header @copying -Copyright @copyright{} 1988-2013 Free Software Foundation, Inc. +Copyright @copyright{} 1988-2014 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or @@ -143,12 +143,12 @@ Additional tutorial information is linked to from @include sourcebuild.texi @include options.texi @include passes.texi -@include rtl.texi @include generic.texi @include gimple.texi @include tree-ssa.texi -@include loop.texi +@include rtl.texi @include cfg.texi +@include loop.texi @include md.texi @include tm.texi @include hostconfig.texi diff --git a/gcc/doc/gcov.texi b/gcc/doc/gcov.texi index 00c7d1d4f0e..a108e52d616 100644 --- a/gcc/doc/gcov.texi +++ b/gcc/doc/gcov.texi @@ -1,10 +1,10 @@ -@c Copyright (C) 1996-2013 Free Software Foundation, Inc. +@c Copyright (C) 1996-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @ignore @c man begin COPYRIGHT -Copyright @copyright{} 1996-2013 Free Software Foundation, Inc. +Copyright @copyright{} 1996-2014 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or diff --git a/gcc/doc/generic.texi b/gcc/doc/generic.texi index 534018e289a..d56a0d33e90 100644 --- a/gcc/doc/generic.texi +++ b/gcc/doc/generic.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2004-2013 Free Software Foundation, Inc. +@c Copyright (C) 2004-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/gimple.texi b/gcc/doc/gimple.texi index 7bd9fd51b78..714addaec7d 100644 --- a/gcc/doc/gimple.texi +++ b/gcc/doc/gimple.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2008-2013 Free Software Foundation, Inc. +@c Copyright (C) 2008-2014 Free Software Foundation, Inc. @c Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/gty.texi b/gcc/doc/gty.texi index a64d110a980..d32ac00e48e 100644 --- a/gcc/doc/gty.texi +++ b/gcc/doc/gty.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2002-2013 Free Software Foundation, Inc. +@c Copyright (C) 2002-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/headerdirs.texi b/gcc/doc/headerdirs.texi index 05422bfe902..2b936f561af 100644 --- a/gcc/doc/headerdirs.texi +++ b/gcc/doc/headerdirs.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/hostconfig.texi b/gcc/doc/hostconfig.texi index bd9a333e490..361f2ce5179 100644 --- a/gcc/doc/hostconfig.texi +++ b/gcc/doc/hostconfig.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gccint.texi. diff --git a/gcc/doc/implement-c.texi b/gcc/doc/implement-c.texi index 974546c1ca8..2ddae637dec 100644 --- a/gcc/doc/implement-c.texi +++ b/gcc/doc/implement-c.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2001-2013 Free Software Foundation, Inc. +@c Copyright (C) 2001-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/implement-cxx.texi b/gcc/doc/implement-cxx.texi index 43a8a597ab6..50efcc39b6d 100644 --- a/gcc/doc/implement-cxx.texi +++ b/gcc/doc/implement-cxx.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2009-2013 Free Software Foundation, Inc. +@c Copyright (C) 2009-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/include/gcc-common.texi b/gcc/doc/include/gcc-common.texi index 17999e5d547..7ce583e884e 100644 --- a/gcc/doc/include/gcc-common.texi +++ b/gcc/doc/include/gcc-common.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2001-2013 Free Software Foundation, Inc. +@c Copyright (C) 2001-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/install-old.texi b/gcc/doc/install-old.texi index 18e5479f8a9..5c993bdecb8 100644 --- a/gcc/doc/install-old.texi +++ b/gcc/doc/install-old.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file install.texi. diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 71aa7fc9866..67586fff446 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -44,7 +44,7 @@ @settitle Installing GCC: GNU Free Documentation License @end ifset -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c *** Converted to texinfo by Dean Wakerley, dean@wakerley.com @c IMPORTANT: whenever you modify this file, run `install.texi2html' to @@ -69,7 +69,7 @@ @c Part 2 Summary Description and Copyright @copying -Copyright @copyright{} 1988-2013 Free Software Foundation, Inc. +Copyright @copyright{} 1988-2014 Free Software Foundation, Inc. @sp 1 Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or diff --git a/gcc/doc/install.texi2html b/gcc/doc/install.texi2html index f664397abee..87ee6b71881 100755 --- a/gcc/doc/install.texi2html +++ b/gcc/doc/install.texi2html @@ -5,7 +5,7 @@ # $SOURCEDIR and $DESTDIR, resp., refer to the directory containing # the texinfo source and the directory to put the HTML version in. # -# Copyright (C) 2001-2013 Free Software Foundation, Inc. +# Copyright (C) 2001-2014 Free Software Foundation, Inc. # Originally by Gerald Pfeifer <pfeifer@dbai.tuwien.ac.at>, June 2001. # # This file is part of GCC. diff --git a/gcc/doc/interface.texi b/gcc/doc/interface.texi index 65ca674f654..c2f25e84ad2 100644 --- a/gcc/doc/interface.texi +++ b/gcc/doc/interface.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b655a6411b1..ae4d5297646 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -8,7 +8,7 @@ @c man end @c man begin COPYRIGHT -Copyright @copyright{} 1988-2013 Free Software Foundation, Inc. +Copyright @copyright{} 1988-2014 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or @@ -161,7 +161,7 @@ in the following sections. -pipe -pass-exit-codes @gol -x @var{language} -v -### --help@r{[}=@var{class}@r{[},@dots{}@r{]]} --target-help @gol --version -wrapper @@@var{file} -fplugin=@var{file} -fplugin-arg-@var{name}=@var{arg} @gol --fdump-ada-spec@r{[}-slim@r{]} -fada-spec-parent=@var{arg} -fdump-go-spec=@var{file}} +-fdump-ada-spec@r{[}-slim@r{]} -fada-spec-parent=@var{unit} -fdump-go-spec=@var{file}} @item C Language Options @xref{C Dialect Options,,Options Controlling C Dialect}. @@ -394,7 +394,7 @@ Objective-C and Objective-C++ Dialects}. -fprefetch-loop-arrays -fprofile-report @gol -fprofile-correction -fprofile-dir=@var{path} -fprofile-generate @gol -fprofile-generate=@var{path} @gol --fprofile-use -fprofile-use=@var{path} -fprofile-values @gol +-fprofile-use -fprofile-use=@var{path} -fprofile-values -fprofile-reorder-functions @gol -freciprocal-math -free -frename-registers -freorder-blocks @gol -freorder-blocks-and-partition -freorder-functions @gol -frerun-cse-after-loop -freschedule-modulo-scheduled-loops @gol @@ -666,7 +666,7 @@ Objective-C and Objective-C++ Dialects}. -mrecip -mrecip=@var{opt} @gol -mvzeroupper -mprefer-avx128 @gol -mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol --mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd @gol +-mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd -msha @gol -maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol -msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol -mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mthreads @gol @@ -840,6 +840,16 @@ Objective-C and Objective-C++ Dialects}. -mforce-fp-as-gp -mforbid-fp-as-gp @gol -mex9 -mctor-dtor -mrelax} +@emph{Nios II Options} +@gccoptlist{-G @var{num} -mgpopt -mno-gpopt -mel -meb @gol +-mno-bypass-cache -mbypass-cache @gol +-mno-cache-volatile -mcache-volatile @gol +-mno-fast-sw-div -mfast-sw-div @gol +-mhw-mul -mno-hw-mul -mhw-mulx -mno-hw-mulx -mno-hw-div -mhw-div @gol +-mcustom-@var{insn}=@var{N} -mno-custom-@var{insn} @gol +-mcustom-fpu-cfg=@var{name} @gol +-mhal -msmallc -msys-crt0=@var{name} -msys-lib=@var{name}} + @emph{PDP-11 Options} @gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol -mbcopy -mbcopy-builtin -mint32 -mno-int16 @gol @@ -933,7 +943,8 @@ See RS/6000 and PowerPC Options. -msmall-exec -mno-small-exec -mmvcle -mno-mvcle @gol -m64 -m31 -mdebug -mno-debug -mesa -mzarch @gol -mtpf-trace -mno-tpf-trace -mfused-madd -mno-fused-madd @gol --mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard} +-mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard @gol +-mhotpatch[=@var{halfwords}] -mno-hotpatch} @emph{Score Options} @gccoptlist{-meb -mel @gol @@ -1517,10 +1528,15 @@ for the plugin called @var{name}. @item -fdump-ada-spec@r{[}-slim@r{]} @opindex fdump-ada-spec -For C and C++ source and include files, generate corresponding Ada -specs. @xref{Generating Ada Bindings for C and C++ headers,,, gnat_ugn, +For C and C++ source and include files, generate corresponding Ada specs. +@xref{Generating Ada Bindings for C and C++ headers,,, gnat_ugn, GNAT User's Guide}, which provides detailed documentation on this feature. +@item -fada-spec-parent=@var{unit} +@opindex fada-spec-parent +In conjunction with @option{-fdump-ada-spec@r{[}-slim@r{]}} above, generate +Ada specs as child units of parent @var{unit}. + @item -fdump-go-spec=@var{file} @opindex fdump-go-spec For input files in any language, generate corresponding Go @@ -5977,9 +5993,9 @@ Dump after generating the function prologues and epilogues. @option{-fdump-rtl-sched1} and @option{-fdump-rtl-sched2} enable dumping after the basic block scheduling passes. -@item -fdump-rtl-see -@opindex fdump-rtl-see -Dump after sign extension elimination. +@item -fdump-rtl-ree +@opindex fdump-rtl-ree +Dump after sign/zero extension elimination. @item -fdump-rtl-seqabstr @opindex fdump-rtl-seqabstr @@ -6506,7 +6522,7 @@ gcc -fopt-info-vec-missed=vec.miss -fopt-info-loop-optimized=loop.opt Here the two output filenames @file{vec.miss} and @file{loop.opt} are in conflict since only one output file is allowed. In this case, only the first option takes effect and the subsequent options are -ignored. Thus only the @file{vec.miss} is produced which cotaints +ignored. Thus only the @file{vec.miss} is produced which contains dumps from the vectorizer about missed opportunities. @item -frandom-seed=@var{string} @@ -7338,6 +7354,18 @@ branch-less equivalents. Enabled at levels @option{-O}, @option{-O2}, @option{-O3}, @option{-Os}. +@item -fdeclone-ctor-dtor +@opindex fdeclone-ctor-dtor +The C++ ABI requires multiple entry points for constructors and +destructors: one for a base subobject, one for a complete object, and +one for a virtual destructor that calls operator delete afterwards. +For a hierarchy with virtual bases, the base and complete variants are +clones, which means two copies of the function. With this option, the +base and complete variants are changed to be thunks that call a common +implementation. + +Enabled by @option{-Os}. + @item -fdelete-null-pointer-checks @opindex fdelete-null-pointer-checks Assume that programs cannot safely dereference null pointers, and that @@ -9071,6 +9099,14 @@ from profiling values of expressions for usage in optimizations. Enabled with @option{-fprofile-generate} and @option{-fprofile-use}. +@item -fprofile-reoder-functions +@opindex fprofile-reorder-functions +Function reordering based on profile instrumentation collects +first time of execution of a function and orders these functions +in ascending order. + +Enabled with @option{-fprofile-use}. + @item -fvpt @opindex fvpt If combined with @option{-fprofile-arcs}, this option instructs the compiler @@ -11204,6 +11240,7 @@ platform. * Moxie Options:: * MSP430 Options:: * NDS32 Options:: +* Nios II Options:: * PDP-11 Options:: * picoChip Options:: * PowerPC Options:: @@ -11326,6 +11363,9 @@ possible values for @var{cpu} are @samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}. The possible values for @var{feature} are documented in the sub-section below. +Additionally, this option can specify that the target is a big.LITTLE system. +The only possible value is @samp{cortex-a57.cortex-a53}. + Where conflicting feature modifiers are specified, the right-most feature is used. @@ -12157,7 +12197,8 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp}, @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, -@samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a53}, @samp{cortex-r4}, +@samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a53}, @samp{cortex-a57}, +@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m4}, @samp{cortex-m3}, @samp{cortex-m1}, @@ -12168,6 +12209,9 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}. +Additionally, this option can specify that GCC should tune the performance +of the code for a big.LITTLE system. Permissible names are: +@samp{cortex-a15.cortex-a7}, @samp{cortex-a57.cortex-a53}. @option{-mcpu=generic-@var{arch}} is also permissible, and is equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. @@ -12212,9 +12256,12 @@ of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, @samp{armv6}, @samp{armv6j}, @samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m}, @samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, -@samp{armv8-a}, +@samp{armv8-a}, @samp{armv8-a+crc}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. +@option{-march=armv8-a+crc} enables code generation for the ARMv8-A +architecture together with the optional CRC32 extensions. + @option{-march=native} causes the compiler to auto-detect the architecture of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is @@ -14629,29 +14676,38 @@ SSE2 and SSE3 instruction set support. Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. -@item corei7 -Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, +@item nehalem +Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and POPCNT instruction set support. -@item corei7-avx -Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, +@item westmere +Intel Westmere CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES and PCLMUL instruction set support. + +@item sandybridge +Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support. -@item core-avx-i -Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, +@item ivybridge +Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction set support. -@item core-avx2 -Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +@item haswell +Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2 and F16C instruction set support. -@item atom -Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3 +@item broadwell +Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support. + +@item bonnell +Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. -@item slm +@item silvermont Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support. @@ -15136,6 +15192,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @itemx -mno-avx512er @itemx -mavx512cd @itemx -mno-avx512cd +@itemx -msha +@itemx -mno-sha @itemx -maes @itemx -mno-aes @itemx -mpclmul @@ -15184,8 +15242,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @opindex mno-3dnow These switches enable or disable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD, -AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, BMI, BMI2, -FXSR, XSAVE, XSAVEOPT, LZCNT, RTM or 3DNow!@: +SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, +BMI, BMI2, FXSR, XSAVE, XSAVEOPT, LZCNT, RTM, or 3DNow!@: extended instruction sets. These extensions are also available as built-in functions: see @ref{X86 Built-in Functions}, for details of the functions enabled and @@ -18169,6 +18227,285 @@ Guide linker to relax instructions. @end table +@node Nios II Options +@subsection Nios II Options +@cindex Nios II options +@cindex Altera Nios II options + +These are the options defined for the Altera Nios II processor. + +@table @gcctabopt + +@item -G @var{num} +@opindex G +@cindex smaller data references +Put global and static objects less than or equal to @var{num} bytes +into the small data or BSS sections instead of the normal data or BSS +sections. The default value of @var{num} is 8. + +@item -mgpopt +@itemx -mno-gpopt +@opindex mgpopt +@opindex mno-gpopt +Generate (do not generate) GP-relative accesses for objects in the +small data or BSS sections. The default is @option{-mgpopt} except +when @option{-fpic} or @option{-fPIC} is specified to generate +position-independent code. Note that the Nios II ABI does not permit +GP-relative accesses from shared libraries. + +You may need to specify @option{-mno-gpopt} explicitly when building +programs that include large amounts of small data, including large +GOT data sections. In this case, the 16-bit offset for GP-relative +addressing may not be large enough to allow access to the entire +small data section. + +@item -mel +@itemx -meb +@opindex mel +@opindex meb +Generate little-endian (default) or big-endian (experimental) code, +respectively. + +@item -mbypass-cache +@itemx -mno-bypass-cache +@opindex mno-bypass-cache +@opindex mbypass-cache +Force all load and store instructions to always bypass cache by +using I/O variants of the instructions. The default is not to +bypass the cache. + +@item -mno-cache-volatile +@itemx -mcache-volatile +@opindex mcache-volatile +@opindex mno-cache-volatile +Volatile memory access bypass the cache using the I/O variants of +the load and store instructions. The default is not to bypass the cache. + +@item -mno-fast-sw-div +@itemx -mfast-sw-div +@opindex mno-fast-sw-div +@opindex mfast-sw-div +Do not use table-based fast divide for small numbers. The default +is to use the fast divide at @option{-O3} and above. + +@item -mno-hw-mul +@itemx -mhw-mul +@itemx -mno-hw-mulx +@itemx -mhw-mulx +@itemx -mno-hw-div +@itemx -mhw-div +@opindex mno-hw-mul +@opindex mhw-mul +@opindex mno-hw-mulx +@opindex mhw-mulx +@opindex mno-hw-div +@opindex mhw-div +Enable or disable emitting @code{mul}, @code{mulx} and @code{div} family of +instructions by the compiler. The default is to emit @code{mul} +and not emit @code{div} and @code{mulx}. + +@item -mcustom-@var{insn}=@var{N} +@itemx -mno-custom-@var{insn} +@opindex mcustom-@var{insn} +@opindex mno-custom-@var{insn} +Each @option{-mcustom-@var{insn}=@var{N}} option enables use of a +custom instruction with encoding @var{N} when generating code that uses +@var{insn}. For example, @code{-mcustom-fadds=253} generates custom +instruction 253 for single-precision floating-point add operations instead +of the default behavior of using a library call. + +The following values of @var{insn} are supported. Except as otherwise +noted, floating-point operations are expected to be implemented with +normal IEEE 754 semantics and correspond directly to the C operators or the +equivalent GCC built-in functions (@pxref{Other Builtins}). + +Single-precision floating point: +@table @asis + +@item @samp{fadds}, @samp{fsubs}, @samp{fdivs}, @samp{fmuls} +Binary arithmetic operations. + +@item @samp{fnegs} +Unary negation. + +@item @samp{fabss} +Unary absolute value. + +@item @samp{fcmpeqs}, @samp{fcmpges}, @samp{fcmpgts}, @samp{fcmples}, @samp{fcmplts}, @samp{fcmpnes} +Comparison operations. + +@item @samp{fmins}, @samp{fmaxs} +Floating-point minimum and maximum. These instructions are only +generated if @option{-ffinite-math-only} is specified. + +@item @samp{fsqrts} +Unary square root operation. + +@item @samp{fcoss}, @samp{fsins}, @samp{ftans}, @samp{fatans}, @samp{fexps}, @samp{flogs} +Floating-point trigonometric and exponential functions. These instructions +are only generated if @option{-funsafe-math-optimizations} is also specified. + +@end table + +Double-precision floating point: +@table @asis + +@item @samp{faddd}, @samp{fsubd}, @samp{fdivd}, @samp{fmuld} +Binary arithmetic operations. + +@item @samp{fnegd} +Unary negation. + +@item @samp{fabsd} +Unary absolute value. + +@item @samp{fcmpeqd}, @samp{fcmpged}, @samp{fcmpgtd}, @samp{fcmpled}, @samp{fcmpltd}, @samp{fcmpned} +Comparison operations. + +@item @samp{fmind}, @samp{fmaxd} +Double-precision minimum and maximum. These instructions are only +generated if @option{-ffinite-math-only} is specified. + +@item @samp{fsqrtd} +Unary square root operation. + +@item @samp{fcosd}, @samp{fsind}, @samp{ftand}, @samp{fatand}, @samp{fexpd}, @samp{flogd} +Double-precision trigonometric and exponential functions. These instructions +are only generated if @option{-funsafe-math-optimizations} is also specified. + +@end table + +Conversions: +@table @asis +@item @samp{fextsd} +Conversion from single precision to double precision. + +@item @samp{ftruncds} +Conversion from double precision to single precision. + +@item @samp{fixsi}, @samp{fixsu}, @samp{fixdi}, @samp{fixdu} +Conversion from floating point to signed or unsigned integer types, with +truncation towards zero. + +@item @samp{floatis}, @samp{floatus}, @samp{floatid}, @samp{floatud} +Conversion from signed or unsigned integer types to floating-point types. + +@end table + +In addition, all of the following transfer instructions for internal +registers X and Y must be provided to use any of the double-precision +floating-point instructions. Custom instructions taking two +double-precision source operands expect the first operand in the +64-bit register X. The other operand (or only operand of a unary +operation) is given to the custom arithmetic instruction with the +least significant half in source register @var{src1} and the most +significant half in @var{src2}. A custom instruction that returns a +double-precision result returns the most significant 32 bits in the +destination register and the other half in 32-bit register Y. +GCC automatically generates the necessary code sequences to write +register X and/or read register Y when double-precision floating-point +instructions are used. + +@table @asis + +@item @samp{fwrx} +Write @var{src1} into the least significant half of X and @var{src2} into +the most significant half of X. + +@item @samp{fwry} +Write @var{src1} into Y. + +@item @samp{frdxhi}, @samp{frdxlo} +Read the most or least (respectively) significant half of X and store it in +@var{dest}. + +@item @samp{frdy} +Read the value of Y and store it into @var{dest}. +@end table + +Note that you can gain more local control over generation of Nios II custom +instructions by using the @code{target("custom-@var{insn}=@var{N}")} +and @code{target("no-custom-@var{insn}")} function attributes +(@pxref{Function Attributes}) +or pragmas (@pxref{Function Specific Option Pragmas}). + +@item -mcustom-fpu-cfg=@var{name} +@opindex mcustom-fpu-cfg + +This option enables a predefined, named set of custom instruction encodings +(see @option{-mcustom-@var{insn}} above). +Currently, the following sets are defined: + +@option{-mcustom-fpu-cfg=60-1} is equivalent to: +@gccoptlist{-mcustom-fmuls=252 @gol +-mcustom-fadds=253 @gol +-mcustom-fsubs=254 @gol +-fsingle-precision-constant} + +@option{-mcustom-fpu-cfg=60-2} is equivalent to: +@gccoptlist{-mcustom-fmuls=252 @gol +-mcustom-fadds=253 @gol +-mcustom-fsubs=254 @gol +-mcustom-fdivs=255 @gol +-fsingle-precision-constant} + +@option{-mcustom-fpu-cfg=72-3} is equivalent to: +@gccoptlist{-mcustom-floatus=243 @gol +-mcustom-fixsi=244 @gol +-mcustom-floatis=245 @gol +-mcustom-fcmpgts=246 @gol +-mcustom-fcmples=249 @gol +-mcustom-fcmpeqs=250 @gol +-mcustom-fcmpnes=251 @gol +-mcustom-fmuls=252 @gol +-mcustom-fadds=253 @gol +-mcustom-fsubs=254 @gol +-mcustom-fdivs=255 @gol +-fsingle-precision-constant} + +Custom instruction assignments given by individual +@option{-mcustom-@var{insn}=} options override those given by +@option{-mcustom-fpu-cfg=}, regardless of the +order of the options on the command line. + +Note that you can gain more local control over selection of a FPU +configuration by using the @code{target("custom-fpu-cfg=@var{name}")} +function attribute (@pxref{Function Attributes}) +or pragma (@pxref{Function Specific Option Pragmas}). + +@end table + +These additional @samp{-m} options are available for the Altera Nios II +ELF (bare-metal) target: + +@table @gcctabopt + +@item -mhal +@opindex mhal +Link with HAL BSP. This suppresses linking with the GCC-provided C runtime +startup and termination code, and is typically used in conjunction with +@option{-msys-crt0=} to specify the location of the alternate startup code +provided by the HAL BSP. + +@item -msmallc +@opindex msmallc +Link with a limited version of the C library, @option{-lsmallc}, rather than +Newlib. + +@item -msys-crt0=@var{startfile} +@opindex msys-crt0 +@var{startfile} is the file name of the startfile (crt0) to use +when linking. This option is only useful in conjunction with @option{-mhal}. + +@item -msys-lib=@var{systemlib} +@opindex msys-lib +@var{systemlib} is the library name of the library that provides +low-level system calls required by the C library, +e.g. @code{read} and @code{write}. +This option is typically used to link with a library provided by a HAL BSP. + +@end table + @node PDP-11 Options @subsection PDP-11 Options @cindex PDP-11 Options @@ -19762,6 +20099,21 @@ values have to be exact powers of 2 and @var{stack-size} has to be greater than In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by @var{stack-size}. The @var{stack-guard} option can only be used in conjunction with @var{stack-size}. + +@item -mhotpatch[=@var{halfwords}] +@itemx -mno-hotpatch +@opindex mhotpatch +If the hotpatch option is enabled, a ``hot-patching'' function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +Nop instructions (@var{halfwords}, maximum 1000000) or 12 Nop +instructions if no argument is present. Functions with a +hot-patching prologue are never inlined automatically, and a +hot-patching prologue is never generated for functions functions +that are explicitly inline. + +This option can be overridden for individual functions with the +@code{hotpatch} attribute. @end table @node Score Options diff --git a/gcc/doc/languages.texi b/gcc/doc/languages.texi index 788a6957dc1..342314b1387 100644 --- a/gcc/doc/languages.texi +++ b/gcc/doc/languages.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2002-2013 Free Software Foundation, Inc. +@c Copyright (C) 2002-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/libgcc.texi b/gcc/doc/libgcc.texi index d9631b6c642..0dd2ff7deff 100644 --- a/gcc/doc/libgcc.texi +++ b/gcc/doc/libgcc.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2003-2013 Free Software Foundation, Inc. +@c Copyright (C) 2003-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @c Contributed by Aldy Hernandez <aldy@quesejoda.com> diff --git a/gcc/doc/loop.texi b/gcc/doc/loop.texi index b1995c125cf..caa72f2bcab 100644 --- a/gcc/doc/loop.texi +++ b/gcc/doc/loop.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2006-2013 Free Software Foundation, Inc. +@c Copyright (C) 2006-2014 Free Software Foundation, Inc. @c Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/lto.texi b/gcc/doc/lto.texi index d337f5f4bf7..f53df1e933b 100644 --- a/gcc/doc/lto.texi +++ b/gcc/doc/lto.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2010-2013 Free Software Foundation, Inc. +@c Copyright (C) 2010-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @c Contributed by Jan Hubicka <jh@suse.cz> and diff --git a/gcc/doc/makefile.texi b/gcc/doc/makefile.texi index 437a02f18a2..18b1c682e81 100644 --- a/gcc/doc/makefile.texi +++ b/gcc/doc/makefile.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2001-2013 Free Software Foundation, Inc. +@c Copyright (C) 2001-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 44a91830b48..dddff7fedce 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -3233,6 +3233,52 @@ Memory constraint for 45 format. Memory constraint for 37 format. @end table +@item Nios II family---@file{config/nios2/constraints.md} +@table @code + +@item I +Integer that is valid as an immediate operand in an +instruction taking a signed 16-bit number. Range +@minus{}32768 to 32767. + +@item J +Integer that is valid as an immediate operand in an +instruction taking an unsigned 16-bit number. Range +0 to 65535. + +@item K +Integer that is valid as an immediate operand in an +instruction taking only the upper 16-bits of a +32-bit number. Range 32-bit numbers with the lower +16-bits being 0. + +@item L +Integer that is valid as an immediate operand for a +shift instruction. Range 0 to 31. + +@item M +Integer that is valid as an immediate operand for +only the value 0. Can be used in conjunction with +the format modifier @code{z} to use @code{r0} +instead of @code{0} in the assembly output. + +@item N +Integer that is valid as an immediate operand for +a custom instruction opcode. Range 0 to 255. + +@item S +Matches immediates which are addresses in the small +data section and therefore can be added to @code{gp} +as a 16-bit immediate to re-create their 32-bit value. + +@ifset INTERNALS +@item T +A @code{const} wrapped @code{UNSPEC} expression, +representing a supported PIC or TLS relocation. +@end ifset + +@end table + @item PDP-11---@file{config/pdp11/constraints.md} @table @code @item a diff --git a/gcc/doc/objc.texi b/gcc/doc/objc.texi index 5410c7a8ac0..0e73eab4172 100644 --- a/gcc/doc/objc.texi +++ b/gcc/doc/objc.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/optinfo.texi b/gcc/doc/optinfo.texi new file mode 100644 index 00000000000..01095835037 --- /dev/null +++ b/gcc/doc/optinfo.texi @@ -0,0 +1,228 @@ +@c Copyright (C) 2013-2014 Free Software Foundation, Inc. +@c This is part of the GCC manual. +@c For copying conditions, see the file gcc.texi. + +@cindex optimization dumps + +This section is describes dump infrastructure which is common to both +pass dumps as well as optimization dumps. The goal for this +infrastructure is to provide both gcc developers and users detailed +information about various compiler transformations and optimizations. + +@menu +* Dump setup:: Setup of optimization dumps. +* Optimization groups:: Groups made up of optimization passes. +* Dump output verbosity:: How much information to dump. +* Dump files and streams:: Dump output file names and streams. +* Dump types:: Various types of dump functions. +* Dump examples:: Sample usage. +@end menu + +@node Dump setup +@subsection Dump setup +@cindex dump setup + +A dump_manager class is defined in @file{dumpfile.h}. Various passes +register dumping pass-specific information via @code{dump_register} in +@file{passes.c}. During the registration, an optimization pass can +select its optimization group (@pxref{Optimization groups}). After +that optimization information corresponding to the entire group +(presumably from multiple passes) can be output via command-line +switches. Note that if a pass does not fit into any of the pre-defined +groups, it can select @code{OPTGROUP_NONE}. + +Note that in general, a pass need not know its dump output file name, +whether certain flags are enabled, etc. However, for legacy reasons, +passes could also call @code{dump_begin} which returns a stream in +case the particular pass has optimization dumps enabled. A pass could +call @code{dump_end} when the dump has ended. These methods should go +away once all the passes are converted to use the new dump +infrastructure. + +The recommended way to setup the dump output is via @code{dump_start} +and @code{dump_end}. + +@node Optimization groups +@subsection Optimization groups +@cindex optimization groups +The optimization passes are grouped into several categories. Currently +defined categories in @file{dumpfile.h} are + +@ftable @code + +@item OPTGROUP_IPA +IPA optimization passes. Enabled by @option{-ipa} + +@item OPTGROUP_LOOP +Loop optimization passes. Enabled by @option{-loop}. + +@item OPTGROUP_INLINE +Inlining passes. Enabled by @option{-inline}. + +@item OPTGROUP_VEC +Vectorization passes. Enabled by @option{-vec}. + +@item OPTGROUP_OTHER +All other optimization passes which do not fall into one of the above. + +@item OPTGROUP_ALL +All optimization passes. Enabled by @option{-all}. + +@end ftable + +By using groups a user could selectively enable optimization +information only for a group of passes. By default, the optimization +information for all the passes is dumped. + +@node Dump files and streams +@subsection Dump files and streams +@cindex optimization info file names + +There are two separate output streams available for outputting +optimization information from passes. Note that both these streams +accept @code{stderr} and @code{stdout} as valid streams and thus it is +possible to dump output to standard output or error. This is specially +handy for outputting all available information in a single file by +redirecting @code{stderr}. + +@table @code +@item @code{pstream} +This stream is for pass-specific dump output. For example, +@option{-fdump-tree-vect=foo.v} dumps tree vectorization pass output +into the given file name @file{foo.v}. If the file name is not provided, +the default file name is based on the source file and pass number. Note +that one could also use special file names @code{stdout} and +@code{stderr} for dumping to standard output and standard error +respectively. + +@item @code{alt_stream} +This steam is used for printing optimization specific output in +response to the @option{-fopt-info}. Again a file name can be given. If +the file name is not given, it defaults to @code{stderr}. +@end table + +@node Dump output verbosity +@subsection Dump output verbosity +@cindex dump verbosity + +The dump verbosity has the following options + +@table @samp +@item optimized +Print information when an optimization is successfully applied. It is +up to a pass to decide which information is relevant. For example, the +vectorizer passes print the source location of loops which got +successfully vectorized. + +@item missed +Print information about missed optimizations. Individual passes +control which information to include in the output. For example, + +@smallexample +gcc -O2 -ftree-vectorize -fopt-info-vec-missed +@end smallexample + +will print information about missed optimization opportunities from +vectorization passes on stderr. + +@item note +Print verbose information about optimizations, such as certain +transformations, more detailed messages about decisions etc. + +@item all +Print detailed optimization information. This includes +@var{optimized}, @var{missed}, and @var{note}. +@end table + +@node Dump types +@subsection Dump types +@cindex dump types + +@ftable @code + +@item dump_printf + +This is a generic method for doing formatted output. It takes an +additional argument @code{dump_kind} which signifies the type of +dump. This method outputs information only when the dumps are enabled +for this particular @code{dump_kind}. Note that the caller doesn't +need to know if the particular dump is enabled or not, or even the +file name. The caller only needs to decide which dump output +information is relevant, and under what conditions. This determines +the associated flags. + +Consider the following example from @file{loop-unroll.c} where an +informative message about a loop (along with its location) is printed +when any of the following flags is enabled +@itemize @minus + +@item optimization messages +@item RTL dumps +@item detailed dumps + +@end itemize + +@example +int report_flags = MSG_OPTIMIZED_LOCATIONS | TDF_RTL | TDF_DETAILS; +dump_printf_loc (report_flags, locus, + "loop turned into non-loop; it never loops.\n"); +@end example + +@item dump_basic_block +Output basic block. +@item dump_generic_expr +Output generic expression. +@item dump_gimple_stmt +Output gimple statement. + +Note that the above methods also have variants prefixed with +@code{_loc}, such as @code{dump_printf_loc}, which are similar except +they also output the source location information. + +@end ftable + +@node Dump examples +@subsection Dump examples +@cindex dump examples + +@smallexample +gcc -O3 -fopt-info-missed=missed.all +@end smallexample + +outputs missed optimization report from all the passes into +@file{missed.all}. + +As another example, +@smallexample +gcc -O3 -fopt-info-inline-optimized-missed=inline.txt +@end smallexample + +will output information about missed optimizations as well as +optimized locations from all the inlining passes into +@file{inline.txt}. + +If the @var{filename} is provided, then the dumps from all the +applicable optimizations are concatenated into the @file{filename}. +Otherwise the dump is output onto @file{stderr}. If @var{options} is +omitted, it defaults to @option{all-all}, which means dump all +available optimization info from all the passes. In the following +example, all optimization info is output on to @file{stderr}. + +@smallexample +gcc -O3 -fopt-info +@end smallexample + +Note that @option{-fopt-info-vec-missed} behaves the same as +@option{-fopt-info-missed-vec}. + +As another example, consider + +@smallexample +gcc -fopt-info-vec-missed=vec.miss -fopt-info-loop-optimized=loop.opt +@end smallexample + +Here the two output file names @file{vec.miss} and @file{loop.opt} are +in conflict since only one output file is allowed. In this case, only +the first option takes effect and the subsequent options are +ignored. Thus only the @file{vec.miss} is produced which containts +dumps from the vectorizer about missed opportunities. diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi index 73a2a3122f0..ff80dac1921 100644 --- a/gcc/doc/options.texi +++ b/gcc/doc/options.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2003-2013 Free Software Foundation, Inc. +@c Copyright (C) 2003-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/passes.texi b/gcc/doc/passes.texi index 3ed9a4fc204..2727b2c8d02 100644 --- a/gcc/doc/passes.texi +++ b/gcc/doc/passes.texi @@ -1,6 +1,6 @@ @c markers: BUG TODO -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -9,6 +9,7 @@ @cindex passes and files of the compiler @cindex files and passes of the compiler @cindex compiler passes and files +@cindex pass dumps This chapter is dedicated to giving an overview of the optimization and code generation passes of the compiler. In the process, it describes @@ -22,6 +23,7 @@ where near complete. * Pass manager:: Sequencing the optimization passes. * Tree SSA passes:: Optimizations on a high-level representation. * RTL passes:: Optimizations on a low-level representation. +* Optimization info:: Dumping optimization information from passes. @end menu @node Parsing pass @@ -208,6 +210,7 @@ semantic checks), it should return @code{GS_ERROR}. The pass manager is located in @file{passes.c}, @file{tree-optimize.c} and @file{tree-pass.h}. +It processes passes as described in @file{passes.def}. Its job is to run all of the individual passes in the correct order, and take care of standard bookkeeping that applies to every pass. @@ -974,3 +977,7 @@ symbol table format, and @file{vmsdbgout.c} for VMS debug symbol table format. @end itemize + +@node Optimization info +@section Optimization info +@include optinfo.texi diff --git a/gcc/doc/plugins.texi b/gcc/doc/plugins.texi index fc2d754dc0b..f1983808b06 100644 --- a/gcc/doc/plugins.texi +++ b/gcc/doc/plugins.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2009-2013 Free Software Foundation, Inc. +@c Copyright (C) 2009-2014 Free Software Foundation, Inc. @c Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/portability.texi b/gcc/doc/portability.texi index 87eb4baa76e..5c893d400f8 100644 --- a/gcc/doc/portability.texi +++ b/gcc/doc/portability.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi index 995f1086cf5..b521afefc5d 100644 --- a/gcc/doc/rtl.texi +++ b/gcc/doc/rtl.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/service.texi b/gcc/doc/service.texi index 2a6d4310713..f8ab62726f3 100644 --- a/gcc/doc/service.texi +++ b/gcc/doc/service.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 2947ac8fae2..f9bc8805609 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2002-2013 Free Software Foundation, Inc. +@c Copyright (C) 2002-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/standards.texi b/gcc/doc/standards.texi index 3c1f480f3de..f5744c8473a 100644 --- a/gcc/doc/standards.texi +++ b/gcc/doc/standards.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2000-2013 Free Software Foundation, Inc. +@c Copyright (C) 2000-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 4579ad954b4..17ee85946ac 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 26223122b11..b900bf9c94d 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. diff --git a/gcc/doc/tree-ssa.texi b/gcc/doc/tree-ssa.texi index 93f596d07a4..391dba89e5d 100644 --- a/gcc/doc/tree-ssa.texi +++ b/gcc/doc/tree-ssa.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 2004-2013 Free Software Foundation, Inc. +@c Copyright (C) 2004-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -265,15 +265,15 @@ those you are interested in. They are documented in #define SSA_OP_USE 0x01 /* @r{Real USE operands.} */ #define SSA_OP_DEF 0x02 /* @r{Real DEF operands.} */ #define SSA_OP_VUSE 0x04 /* @r{VUSE operands.} */ -#define SSA_OP_VMAYUSE 0x08 /* @r{USE portion of VDEFS.} */ -#define SSA_OP_VDEF 0x10 /* @r{DEF portion of VDEFS.} */ +#define SSA_OP_VDEF 0x08 /* @r{VDEF operands.} */ /* @r{These are commonly grouped operand flags.} */ -#define SSA_OP_VIRTUAL_USES (SSA_OP_VUSE | SSA_OP_VMAYUSE) -#define SSA_OP_VIRTUAL_DEFS (SSA_OP_VDEF) -#define SSA_OP_ALL_USES (SSA_OP_VIRTUAL_USES | SSA_OP_USE) -#define SSA_OP_ALL_DEFS (SSA_OP_VIRTUAL_DEFS | SSA_OP_DEF) -#define SSA_OP_ALL_OPERANDS (SSA_OP_ALL_USES | SSA_OP_ALL_DEFS) +#define SSA_OP_VIRTUAL_USES (SSA_OP_VUSE) +#define SSA_OP_VIRTUAL_DEFS (SSA_OP_VDEF) +#define SSA_OP_ALL_VIRTUALS (SSA_OP_VIRTUAL_USES | SSA_OP_VIRTUAL_DEFS) +#define SSA_OP_ALL_USES (SSA_OP_VIRTUAL_USES | SSA_OP_USE) +#define SSA_OP_ALL_DEFS (SSA_OP_VIRTUAL_DEFS | SSA_OP_DEF) +#define SSA_OP_ALL_OPERANDS (SSA_OP_ALL_USES | SSA_OP_ALL_DEFS) @end smallexample @end enumerate @@ -307,25 +307,10 @@ aren't using operand pointers, use and defs flags can be mixed. @code{VDEF}s are broken into two flags, one for the @code{DEF} portion (@code{SSA_OP_VDEF}) and one for the USE portion -(@code{SSA_OP_VMAYUSE}). If all you want to look at are the -@code{VDEF}s together, there is a fourth iterator macro for this, -which returns both a def_operand_p and a use_operand_p for each -@code{VDEF} in the statement. Note that you don't need any flags for -this one. +(@code{SSA_OP_VUSE}). -@smallexample - use_operand_p use_p; - def_operand_p def_p; - ssa_op_iter iter; - - FOR_EACH_SSA_MAYDEF_OPERAND (def_p, use_p, stmt, iter) - @{ - my_code; - @} -@end smallexample - -There are many examples in the code as well, as well as the -documentation in @file{tree-ssa-operands.h}. +There are many examples in the code, in addition to the documentation +in @file{tree-ssa-operands.h} and @file{ssa-iterators.h}. There are also a couple of variants on the stmt iterators regarding PHI nodes. diff --git a/gcc/doc/trouble.texi b/gcc/doc/trouble.texi index d5b056a618a..620da682d0c 100644 --- a/gcc/doc/trouble.texi +++ b/gcc/doc/trouble.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2013 Free Software Foundation, Inc. +@c Copyright (C) 1988-2014 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. |