invoke.texi (C6X Options): New section.

gcc/
	* doc/invoke.texi (C6X Options): New section.
	* doc/md.texi (TI C6X family): New section.
	* config.gcc: Handle tic6x, in particular tic6x-*-elf and
	tic6x-*-uclinux.
	* longlong.h (add_ssaaaa, __umulsidi3, umul_ppmm,
	count_leading_zeros, count_trailing_zeros, UMUL_TIME, UDIV_TIME):
	Provide C6X definitions.
	* config/c6x/c6x.md: New file.
	* config/c6x/constraints.md: New file.
	* config/c6x/predicates.md: New file.
	* config/c6x/c6x-sched.md.in: New file.
	* config/c6x/c6x-sched.md: New file.
	* config/c6x/gensched.sh: New file.
	* config/c6x/c6x-mult.md.in: New file.
	* config/c6x/genmult.sh: New file.
	* config/c6x/c6x-mult.md: New file.
	* config/c6x/sync.md: New file.
	* config/c6x/c6x-protos.h: New file.
	* config/c6x/sfp-machine.h: New file.
	* config/c6x/c6x.c: New file.
	* config/c6x/c6x.h: New file.
	* config/c6x/crti.s: New file.
	* config/c6x/crtn.s: New file.
	* config/c6x/lib1funcs.asm: New file.
	* config/c6x/c6x-modes.def: New file.
	* config/c6x/genopt.sh: New file.
	* config/c6x/c6x.opt: New file.
	* config/c6x/c6x-tables.opt: New file.
	* config/c6x/c6x-opts.h: New file.
	* config/c6x/c6x-isas.def: New file.
	* config/c6x/elf.h: New file.
	* config/c6x/elf-common.h: New file.
	* config/c6x/uclinux-elf.h: New file.
	* config/c6x/t-c6x: New file.
	* config/c6x/t-c6x-elf: New file.
	* config/c6x/t-c6x-uclinux: New file.
	* config/c6x/t-c6x-softfp: New file.
	* config/c6x/gtd.c: New file.
	* config/c6x/gtf.c: New file.
	* config/c6x/ltd.c: New file.
	* config/c6x/ltf.c: New file.
	* config/c6x/ged.c: New file.
	* config/c6x/gef.c: New file.
	* config/c6x/led.c: New file.
	* config/c6x/lef.c: New file.
	* config/c6x/eqd.c: New file.
	* config/c6x/eqf.c: New file.
	* config/c6x/libgcc-c6xeabi.ver: New file.

contrib/
	* gcc_update: Add C6X generated files.
	* contrib/config-list.mk: Add c6x-elf and c6x-uclinux.

libgcc/
	* config.host: Handle tic6x-*-*.
	* config/c6x/c6x-abi.h: New file.

From-SVN: r176308

5 files changed, 187 insertions, 2 deletions

diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi
index 4096879a1c7..939f6dea1dd 100644
--- a/gcc/doc/contrib.texi
+++ b/gcc/doc/contrib.texi
@@ -806,8 +806,8 @@ Tobias Schl@"uter for work on GNU Fortran.
 
 @item
 Bernd Schmidt for various code generation improvements and major
-work in the reload pass as well a serving as release manager for
-GCC 2.95.3.
+work in the reload pass, serving as release manager for
+GCC 2.95.3, and work on the Blackfin and C6X ports.
 
 @item
 Peter Schmid for constant testing of libstdc++---especially application
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index e97e789a752..7cbd68ea906 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7975,6 +7975,7 @@ instructions, but allow the compiler to schedule those calls.
 * RX Built-in Functions::
 * SPARC VIS Built-in Functions::
 * SPU Built-in Functions::
+* TI C6X Built-in Functions::
 @end menu
 
 @node Alpha Built-in Functions
@@ -12793,6 +12794,45 @@ specification is supported. Internally, GCC uses built-in functions to
 implement the required functionality, but these are not supported and
 are subject to change without notice.
 
+@node TI C6X Built-in Functions
+@subsection TI C6X Built-in Functions
+
+GCC provides intrinsics to access certain instructions of the TI C6X
+processors.  These intrinsics, listed below, are available after
+inclusion of the @code{c6x_intrinsics.h} header file.  They map directly
+to C6X instructions.
+
+@smallexample
+
+int _sadd (int, int)
+int _ssub (int, int)
+int _sadd2 (int, int)
+int _ssub2 (int, int)
+long long _mpy2 (int, int)
+long long _smpy2 (int, int)
+int _add4 (int, int)
+int _sub4 (int, int)
+int _saddu4 (int, int)
+
+int _smpy (int, int)
+int _smpyh (int, int)
+int _smpyhl (int, int)
+int _smpylh (int, int)
+
+int _sshl (int, int)
+int _subc (int, int)
+
+int _avg2 (int, int)
+int _avgu4 (int, int)
+
+int _clrr (int, int)
+int _extr (int, int)
+int _extru (int, int)
+int _abs (int)
+int _abs2 (int)
+
+@end smallexample
+
 @node Target Format Checks
 @section Format Checks Specific to Particular Target Machines
 
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 9834728f838..811bf3d7ccd 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -3071,6 +3071,8 @@ information are.
 @item
 @uref{#sparcv9-x-solaris2,,sparcv9-*-solaris2*}
 @item
+@uref{#c6x-x-x,,c6x-*-*}
+@item
 @uref{#x-x-vxworks,,*-*-vxworks*}
 @item
 @uref{#x86-64-x-x,,x86_64-*-*, amd64-*-*}
@@ -4382,6 +4384,13 @@ This is a synonym for @samp{sparc64-*-solaris2*}.
 @html
 <hr />
 @end html
+@heading @anchor{c6x-x-x}c6x-*-*
+
+The C6X family of processors. This port requires binutils-2.22 or newer.
+
+@html
+<hr />
+@end html
 @heading @anchor{x-x-vxworks}*-*-vxworks*
 Support for VxWorks is in flux.  At present GCC supports @emph{only} the
 very recent VxWorks 5.5 (aka Tornado 2.2) release, and only on PowerPC@.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 39c805b04d3..7541e3a92f3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -496,6 +496,10 @@ Objective-C and Objective-C++ Dialects}.
 -mfast-fp -minline-plt -mmulticore  -mcorea  -mcoreb  -msdram @gol
 -micplb}
 
+@emph{C6X Options}
+@gccoptlist{-mbig-endian  -mlittle-endian -march=@var{cpu} @gol
+-msim -msdata=@var{sdata-type}}
+
 @emph{CRIS Options}
 @gccoptlist{-mcpu=@var{cpu}  -march=@var{cpu}  -mtune=@var{cpu} @gol
 -mmax-stack-frame=@var{n}  -melinux-stacksize=@var{n} @gol
@@ -10091,6 +10095,7 @@ platform.
 * ARM Options::
 * AVR Options::
 * Blackfin Options::
+* C6X Options::
 * CRIS Options::
 * Darwin Options::
 * DEC Alpha Options::
@@ -10755,6 +10760,54 @@ anomaly workarounds.  For Linux targets, the default is to assume ICPLBs
 are enabled; for standalone applications the default is off.
 @end table
 
+@node C6X Options
+@subsection C6X Options
+@cindex C6X Options
+
+@table @gcctabopt
+@item -march=@var{name}
+@opindex march
+This specifies the name of the target architecture.  GCC uses this
+name to determine what kind of instructions it can emit when generating
+assembly code.  Permissible names are: @samp{c62x},
+@samp{c64x}, @samp{c64x+}, @samp{c67x}, @samp{c67x+}, @samp{c674x}.
+
+@item -mbig-endian
+@opindex mbig-endian
+Generate code for a big endian target.
+
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate code for a little endian target.  This is the default.
+
+@item -msim
+@opindex msim
+Choose startup files and linker script suitable for the simulator.
+
+@item -msdata=default
+@opindex msdata=default
+Put small global and static data in the @samp{.neardata} section,
+which is pointed to by register @code{B14}.  Put small uninitialized
+global and static data in the @samp{.bss} section, which is adjacent
+to the @samp{.neardata} section.  Put small read-only data into the
+@samp{.rodata} section.  The corresponding sections used for large
+pieces of data are @samp{.fardata}, @samp{.far} and @samp{.const}.
+
+@item -msdata=all
+@opindex msdata=all
+Put all data, not just small objets, into the sections reserved for
+small data, and use addressing relative to the @code{B14} register to
+access them.
+
+@item -msdata=none
+@opindex msdata=none
+Make no use of the sections reserved for small data, and use absolute
+addresses to access all data.  Put all initialized global and static
+data in the @samp{.fardata} section, and all uninitialized data in the
+@samp{.far} section.  Put all constant data into the @samp{.const}
+section.
+@end table
+
 @node CRIS Options
 @subsection CRIS Options
 @cindex CRIS Options
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index abe51f80727..23047ca45aa 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3304,6 +3304,89 @@ The constant 0.
 
 @end table
 
+@item TI C6X family---@file{config/c6x/constraints.md}
+@table @code
+@item a
+Register file A (A0--A31).
+
+@item b
+Register file B (B0--B31).
+
+@item A
+Predicate registers in register file A (A0--A2 on C64X and
+higher, A1 and A2 otherwise).
+
+@item B
+Predicate registers in register file B (B0--B2).
+
+@item C
+A call-used register in register file B (B0--B9, B16--B31).
+
+@item Da
+Register file A, excluding predicate registers (A3--A31,
+plus A0 if not C64X or higher).
+
+@item Db
+Register file B, excluding predicate registers (B3--B31).
+
+@item Iu4
+Integer constant in the range 0 @dots{} 15.
+
+@item Iu5
+Integer constant in the range 0 @dots{} 31.
+
+@item In5
+Integer constant in the range @minus{}31 @dots{} 0.
+
+@item Is5
+Integer constant in the range @minus{}16 @dots{} 15.
+
+@item I5x
+Integer constant that can be the operand of an ADDA or a SUBA insn.
+
+@item IuB
+Integer constant in the range 0 @dots{} 65535.
+
+@item IsB
+Integer constant in the range @minus{}32768 @dots{} 32767.
+
+@item IsC
+Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
+
+@item Jc
+Integer constant that is a valid mask for the clr instruction.
+
+@item Js
+Integer constant that is a valid mask for the set instruction.
+
+@item Q
+Memory location with A base register.
+
+@item R
+Memory location with B base register.
+
+@ifset INTERNALS
+@item S0
+On C64x+ targets, a GP-relative small data reference.
+
+@item S1
+Any kind of @code{SYMBOL_REF}, for use in a call address.
+
+@item Si
+Any kind of immediate operand, unless it matches the S0 constraint.
+
+@item T
+Memory location with B base register, but not using a long offset.
+
+@item W
+A memory operand with an address that can't be used in an unaligned access.
+
+@end ifset
+@item Z
+Register B14 (aka DP).
+
+@end table
+
 @item Xtensa---@file{config/xtensa/constraints.md}
 @table @code
 @item a