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| author | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2010-08-23 16:47:01 +0000 |
|---|---|---|
| committer | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2010-08-23 16:47:01 +0000 |
| commit | ac3fd8d3a2dacabb312cb0fc78c0b9851063d451 (patch) | |
| tree | 75babdfed5a5d5dbf4490f8815f7461775c5339b /gcc/doc | |
| parent | 79676f03d03605298180b4e8d6ad33fb094fb416 (diff) | |
| download | gcc-ac3fd8d3a2dacabb312cb0fc78c0b9851063d451.tar.gz | |
Update to use -mveclibabi=mass instead of -mmass
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@163471 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 4cdda3dcef9..148117da647 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -788,7 +788,7 @@ See RS/6000 and PowerPC Options. -msdata=@var{opt} -mvxworks -G @var{num} -pthread @gol -mrecip -mrecip=@var{opt} -mno-recip -mrecip-precision -mno-recip-precision @gol --mmass} +-mveclibabi=@var{type}} @emph{RX Options} @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol @@ -15850,12 +15850,13 @@ precision square root estimate instructions are not generated by default on low precision machines, since they do not provide an estimate that converges after three steps. -@item -mmass -@itemx -mno-mass -@opindex mmass -Specifies to use IBM's Mathematical Acceleration Subsystem (MASS) -libraries for vectorizing intrinsics using external libraries. GCC -will currently emit calls to @code{acosd2}, @code{acosf4}, +@item -mveclibabi=@var{type} +@opindex mveclibabi +Specifies the ABI type to use for vectorizing intrinsics using an +external library. The only type supported at present is @code{mass}, +which specifies to use IBM's Mathematical Acceleration Subsystem +(MASS) libraries for vectorizing intrinsics using external libraries. +GCC will currently emit calls to @code{acosd2}, @code{acosf4}, @code{acoshd2}, @code{acoshf4}, @code{asind2}, @code{asinf4}, @code{asinhd2}, @code{asinhf4}, @code{atan2d2}, @code{atan2f4}, @code{atand2}, @code{atanf4}, @code{atanhd2}, @code{atanhf4}, |