summaryrefslogtreecommitdiff
path: root/gcc/doc/tm.texi.in
diff options
context:
space:
mode:
authorrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>2015-10-27 19:59:41 +0000
committerrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>2015-10-27 19:59:41 +0000
commite94743fac27ba9a742870dbca56ddc27c1499e8f (patch)
treeeec2e90ceb0a5636cb3bfde359439074db6769a1 /gcc/doc/tm.texi.in
parent7ee34ff60c19b6e032249b3ec82a6a4d2a40ed30 (diff)
downloadgcc-e94743fac27ba9a742870dbca56ddc27c1499e8f.tar.gz
PR rtl-opt/67609
* config/i386/i386.c (ix86_cannot_change_mode_class): Disallow narrowing subregs on SSE and MMX registers. * doc/tm.texi.in (CANNOT_CHANGE_MODE_CLASS): Clarify when subregs that appear to be sub-words of multi-register pseudos must be rejected. * doc/tm.texi: Regenerate. testsuite/ * gcc.target/i386/pr67609-2.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229458 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/doc/tm.texi.in')
-rw-r--r--gcc/doc/tm.texi.in15
1 files changed, 13 insertions, 2 deletions
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 69b6cf90e21..93620ebd325 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -2461,8 +2461,8 @@ in the reload pass.
If defined, a C expression that returns nonzero for a @var{class} for which
a change from mode @var{from} to mode @var{to} is invalid.
-For the example, loading 32-bit integer or floating-point objects into
-floating-point registers on the Alpha extends them to 64 bits.
+For example, loading 32-bit integer or floating-point objects into
+floating-point registers on Alpha extends them to 64 bits.
Therefore loading a 64-bit object and then storing it as a 32-bit object
does not store the low-order 32 bits, as would be the case for a normal
register. Therefore, @file{alpha.h} defines @code{CANNOT_CHANGE_MODE_CLASS}
@@ -2473,6 +2473,17 @@ as below:
(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0)
@end smallexample
+
+Even if storing from a register in mode @var{to} would be valid,
+if both @var{from} and @code{raw_reg_mode} for @var{class} are wider
+than @code{word_mode}, then we must prevent @var{to} narrowing the
+mode. This happens when the middle-end assumes that it can load
+or store pieces of an @var{N}-word pseudo, and that the pseudo will
+eventually be allocated to @var{N} @code{word_mode} hard registers.
+Failure to prevent this kind of mode change will result in the
+entire @code{raw_reg_mode} being modified instead of the partial
+value that the middle-end intended.
+
@end defmac
@hook TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS