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authorrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>2011-10-07 22:41:48 +0000
committerrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>2011-10-07 22:41:48 +0000
commitf480372230f4bfc55d02b48322ed5c96e999d7e0 (patch)
tree485f14b72a67f60b5c3ee61f71970cc2727a2fda /gcc/doc/md.texi
parentc450bad4d485c9ed451a3be37c6a4c5f0d943c5f (diff)
downloadgcc-f480372230f4bfc55d02b48322ed5c96e999d7e0.tar.gz
Rename vshuffle/vec_shuffle to vec_perm.
* doc/extend.texi (__builtin_shuffle): Improve the description to include the modulus of the selector. Mention OpenCL. * doc/md.texi (vec_perm, vec_perm_const): Document named patterns. * tree.def (VEC_PERM_EXPR): Rename from VEC_SHUFFLE_EXPR. * genopinit.c (optabs): Rename vshuffle to vec_perm. * c-typeck.c (c_build_vec_perm_expr): Rename from c_build_vec_shuffle_expr. Update for name changes. * optabs.c (expand_vec_perm_expr_p): Rename from expand_vec_shuffle_expr_p. (expand_vec_perm_expr): Rename from expand_vec_shuffle_expr. * optabs.h (OTI_vec_perm): Rename from DOI_vshuffle. (vec_perm_optab): Rename from vshuffle_optab. * expr.c, gimple-pretty-print.c, gimple.c, gimplify.c, c-tree.h, c-parser.c, tree-cfg.c, tree-inline.c, tree-pretty-print.c, tree-ssa-operands.c, tree-vect-generic.c: Update for name changes. * config/i386/i386.c (ix86_expand_vec_perm): Rename from ix86_expand_vshuffle. * config/i386/i386-protos.h: Update. * config/i386/sse.md (VEC_PERM_AVX2): Rename from VSHUFFLE_AVX2. (vec_perm<VEC_PERM_AVX2>): Rename from vshuffle<VSHUFFLE_AVX2>. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179701 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/doc/md.texi')
-rw-r--r--gcc/doc/md.texi28
1 files changed, 28 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 1aa8552c5d4..b61a99b3df7 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -4028,6 +4028,34 @@ will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
where @var{msk} is computed by element-wise evaluation of the vector
comparison with a truth value of all-ones and a false value of all-zeros.
+@cindex @code{vec_perm@var{m}} instruction pattern
+@item @samp{vec_perm@var{m}}
+Output a (variable) vector permutation. Operand 0 is the destination
+to receive elements from operand 1 and operand 2, which are of mode
+@var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
+vector of the same width and number of elements as mode @var{m}.
+
+The input elements are numbered from 0 in operand 1 through
+@math{2*@var{N}-1} in operand 2. The elements of the selector must
+be computed modulo @math{2*@var{N}}. Note that if
+@code{rtx_equal_p(operand1, operand2)}, this can be implemented
+with just operand 1 and selector elements modulo @var{N}.
+
+@cindex @code{vec_perm_const@var{m}) instruction pattern
+@item @samp{vec_perm_const@var{m}}
+Like @samp{vec_perm} except that the permutation is a compile-time
+constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
+
+Some targets cannot perform a permutation with a variable selector,
+but can efficiently perform a constant permutation. Further, the
+target hook @code{vec_perm_ok} is queried to determine if the
+specific constant permutation is available efficiently; the named
+pattern is never expanded without @code{vec_perm_ok} returning true.
+
+There is no need for a target to supply both @samp{vec_perm@var{m}}
+and @samp{vec_perm_const@var{m}} if the former can trivially implement
+the operation with, say, the vector constant loaded into a register.
+
@cindex @code{push@var{m}1} instruction pattern
@item @samp{push@var{m}1}
Output a push instruction. Operand 0 is value to push. Used only when