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| author | kyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-12-24 11:05:34 +0000 |
|---|---|---|
| committer | kyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-12-24 11:05:34 +0000 |
| commit | 25222ada53f81be760ca579f88459c7aaf211a96 (patch) | |
| tree | 211be33d7501be799b39b9f03a5d06b4b070eff5 /gcc/doc/invoke.texi | |
| parent | 94720cdd2799111ceadf7082dfbaeb063d94436a (diff) | |
| download | gcc-25222ada53f81be760ca579f88459c7aaf211a96.tar.gz | |
Introduce support for PKU instructions.
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_PKU_SET): New.
(OPTION_MASK_ISA_PKU_UNSET): Ditto.
(ix86_handle_option): Handle OPT_mpku.
* config.gcc: Add pkuintrin.h to i[34567]86-*-* and x86_64-*-*
targets.
* config/i386/cpuid.h (host_detect_local_cpu): Detect PKU feature.
* config/i386/i386-c.c (ix86_target_macros_internal): Handle PKU ISA
flag.
* config/i386/i386.c (ix86_target_string): Add "-mpku" to
ix86_target_opts.
(ix86_option_override_internal): Define PTA_PKU, mention new key
in skylake-avx512. Handle new ISA bits.
(ix86_valid_target_attribute_inner_p): Add "pku".
(enum ix86_builtins): Add IX86_BUILTIN_RDPKRU and IX86_BUILTIN_WRPKRU.
(builtin_description bdesc_special_args[]): Add new built-ins.
* config/i386/i386.h (define TARGET_PKU): New.
(define TARGET_PKU_P): Ditto.
* config/i386/i386.md (define_c_enum "unspecv"): Add UNSPEC_PKU.
(define_expand "rdpkru"): New.
(define_insn "*rdpkru"): Ditto.
(define_expand "wrpkru"): Ditto.
(define_insn "*wrpkru"): Ditto.
* config/i386/i386.opt (mpku): Ditto.
* config/i386/pkuintrin.h: New file.
* config/i386/x86intrin.h: Include pkuintrin.h
* doc/extend.texi: Describe new built-ins.
* doc/invoke.texi: Describe new switches.
gcc/testsuite/
* g++.dg/other/i386-2.C: Add -mpku.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/rdpku-1.c: New test.
* gcc.target/i386/sse-12.c: Add -mpku.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-33.c: Ditto.
* gcc.target/i386/wrpku-1.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231944 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cad32c679b7..4e2cf8f7beb 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1103,7 +1103,8 @@ See RS/6000 and PowerPC Options. -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol -mprefetchwt1 -mclflushopt -mxsavec -mxsaves @gol -msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol --mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mmpx -mmwaitx -mclzero -mthreads @gol +-mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mmpx -mmwaitx -mclzero +-mpku -mthreads @gol -mms-bitfields -mno-align-stringops -minline-all-stringops @gol -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol -mmemcpy-strategy=@var{strategy} -mmemset-strategy=@var{strategy} @gol @@ -22625,7 +22626,7 @@ AVX512CD instruction set support. @item skylake-avx512 Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, -SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support. @@ -23247,11 +23248,13 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @need 200 @itemx -mclzero @opindex mclzero +@itemx -mpku +@opindex mpku These switches enable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD, SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA AVX512VBMI, BMI, BMI2, FXSR, -XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX or 3DNow!@: +XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU or 3DNow!@: extended instruction sets. Each has a corresponding @option{-mno-} option to disable use of these instructions. |