gcc/

	Backport from trunk r222767.
	2015-05-04  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.h (TARGET_SUPPORTS_WIDE_INT): New define.
	* config/i386/i386.c (ix86_legitimate_constant_p): Handle TImode
	as CONST_WIDE_INT, not CONST_DOUBLE.
	(ix86_cannot_force_const_mem): Handle CONST_WIDE_INT.
	(output_pic_addr_const): Do not handle VOIDmode CONST_DOUBLEs.
	(ix86_find_base_term): Do not check for CONST_DOUBLE.
	(ix86_print_operand): Do not handle non-FPmode CONST_DOUBLEs.
	(ix86_build_signbit_mask): Rewrite using wide ints.
	(ix86_split_to_parts) [HOST_BITS_PER_WIDE_INT < 64]: Remove.
	(ix86_rtx_costs): Handle CONST_WIDE_INT.
	(find_constant): Ditto.
	* config/i386/i386.md (bts, btr, btc peepholes): Rewrite
	using gen_int_mode.
	* config/i386/predicates.md (x86_64_immediate_operand)
	<case CONST_INT>: Remove HOST_BITS_PER_WIDE_INT == 32 code.
	(x86_64_zext_immediate_operand): Remove CONST_DOUBLE handling.
	<case CONST_INT>: Remove HOST_BITS_PER_WIDE_INT == 32 code.
	(const0_operand): Also match const_wide_int.
	(constm1_operand): Ditto.
	(const1_operand): Ditto.

	gcc/
	Backport from trunk r226328.
	2015-07-28  David Sherwood  <david.sherwood@arm.com>

	* config/arm/arm.c (neon_element_bits, neon_valid_immediate): Call
	GET_MODE_INNER unconditionally.
	* config/spu/spu.c (arith_immediate_p): Likewise.
	* config/i386/i386.c (ix86_build_signbit_mask): Likewise.
	* expmed.c (synth_mult): Remove check for VOIDmode result from
	GET_MODE_INNER.
	(expand_mult_const): Likewise.
	* fold-const.c (fold_binary_loc): Replace call to element_precision
	with call to GET_MODE_PRECISION.
	* genmodes.c (emit_mode_inner_inline): Replace void_mode->name with
	m->name.
	(emit_mode_inner): Likewise.
	* lto-streamer-out.c (lto_write_mode_table): Update GET_MODE_INNER
	result check.
	* machmode.h (GET_MODE_UNIT_SIZE): Simplify.
	(GET_MODE_UNIT_PRECISION): Likewise.
	* rtlanal.c (subreg_get_info): Call GET_MODE_INNER unconditionally.
	* simplify-rtx.c (simplify_immed_subreg): Likewise.
	* stor-layout.c (bitwise_type_for_mode): Update assert.
	(element_precision): Remove.

	gcc/
	Backport from trunk r226403.
	2015-07-30  David Sherwood  <david.sherwood@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_ext<mode>): Replace call to
	GET_MODE_SIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_SIZE (m).
	* config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Likewise.
	* config/arm/arm.c (neon_valid_immediate): Likewise.
	* config/i386/i386.c (classify_argument, ix86_expand_int_vcond)
	(expand_vec_perm_blend, expand_vec_perm_pshufb): Likewise.
	(expand_vec_perm_pshufb2, expand_vec_perm_vpshufb2_vpermq): Likewise.
	(expand_vec_perm_vpshufb2_vpermq): Likewise.
	(expand_vec_perm_vpshufb2_vpermq_even_odd): Likewise.
	(expand_vec_perm_vpshufb4_vpermq2): Likewise.
	* config/i386/sse.md
	(<extract_type>_vinsert<shuffletype><extract_suf>_mask): Likewise.
	(*ssse3_palignr<mode>_perm): Likewise.
	* config/rs6000/rs6000.c (rs6000_complex_function_value): Likewise.
	* config/spu/spu.c (arith_immediate_p): Likewise.
	* simplify-rtx.c (simplify_const_unary_operation): Likewise.
	(simplify_binary_operation_1, simplify_ternary_operation): Likewise.

	gcc/
	Backport from trunk r226936.
	2015-08-17  David Sherwood  <david.sherwood@arm.com>

	* config/arm/arm.c (neon_element_bits): Replace call to
	GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m).
	* config/arm/neon.md (neon_vget_lane<mode>): Likewise.
	(neon_vget_laneu<mode>, neon_vset_lane<mode>): Likewise
	(neon_vdup_lane<mode>): Likewise.
	* config/i386/i386.c (ix86_expand_int_vcond): Likewise.
	(ix86_expand_multi_arg_builtin, ix86_expand_reduc): Likewise.
	(expand_vec_perm_palignr, ix86_expand_sse2_abs): Likewise.
	* config/rs6000/rs6000.c (rs6000_do_expand_vec_perm): Likewise.
	* config/spu/spu.c (arith_immediate_p): Likewise.
	* expmed.c (store_bit_field_1, extract_bit_field_1): Likewise.
	* expr.c (expand_expr_real_2): Likewise.
	* optabs.c (shift_amt_for_vec_perm_mask): Likewise.
	* simplify-rtx.c (simplify_immed_subreg): Likewise.
	* tree-cfg.c (verify_gimple_assign_ternary): Likewise.
	* tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern): Likewise.
	New variable.
	* fold-const.c (fold_binary_loc): Replace call to
	GET_MODE_PRECISION (GET_MODE_INNER (m)) with
	GET_MODE_UNIT_PRECISION (m).

	gcc/
	Backport from trunk r227013.
	2015-08-19  David Sherwood  <david.sherwood@arm.com>

	* genmodes.c (emit_mode_unit_size_inline): New function.
	(emit_mode_unit_precision_inline): New function.
	(emit_insn_modes_h): Emit new #define.  Emit new functions.
	(emit_mode_unit_size): New function.
	(emit_mode_unit_precision): New function.
	(emit_mode_adjustments): Add mode_unit_size adjustments.
	(emit_insn_modes_c): Emit new arrays.
	* machmode.h (GET_MODE_UNIT_SIZE, GET_MODE_UNIT_PRECISION): Update to
	use new inline methods.

Change-Id: Ic5a8a96f8fc5e8adc144ca539430d7c4f463cf35

11 files changed, 91 insertions, 189 deletions

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 6f8b7038739..555f5afb469 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4814,7 +4814,7 @@
   "TARGET_SIMD"
 {
   operands[3] = GEN_INT (INTVAL (operands[3])
-      * GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)));
+      * GET_MODE_UNIT_SIZE (<MODE>mode));
   return "ext\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>, #%3";
 }
   [(set_attr "type" "neon_ext<q>")]
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5d134799d20..4c53f2a3bb4 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -9645,7 +9645,7 @@ aarch64_simd_valid_immediate (rtx op, machine_mode mode, bool inverse,
     }
 
   unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op);
-  unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
+  unsigned int innersize = GET_MODE_UNIT_SIZE (mode);
   unsigned char bytes[16];
   int immtype = -1, matches;
   unsigned int invmask = inverse ? 0xff : 0;
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index f4d09f5624b..6ed68ba6705 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -12323,18 +12323,16 @@ neon_valid_immediate (rtx op, machine_mode mode, int inverse,
   bool vector = GET_CODE (op) == CONST_VECTOR;
 
   if (vector)
-    {
-      n_elts = CONST_VECTOR_NUNITS (op);
-      innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
-    }
+    n_elts = CONST_VECTOR_NUNITS (op);
   else
     {
       n_elts = 1;
       if (mode == VOIDmode)
 	mode = DImode;
-      innersize = GET_MODE_SIZE (mode);
     }
 
+  innersize = GET_MODE_UNIT_SIZE (mode);
+
   /* Vectors of float constants.  */
   if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
     {
@@ -12560,7 +12558,7 @@ neon_immediate_valid_for_shift (rtx op, machine_mode mode,
 				rtx *modconst, int *elementwidth,
 				bool isleftshift)
 {
-  unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
+  unsigned int innersize = GET_MODE_UNIT_SIZE (mode);
   unsigned int n_elts = CONST_VECTOR_NUNITS (op), i;
   unsigned HOST_WIDE_INT last_elt = 0;
   unsigned HOST_WIDE_INT maxshift;
@@ -12667,8 +12665,7 @@ void
 neon_pairwise_reduce (rtx op0, rtx op1, machine_mode mode,
 		      rtx (*reduc) (rtx, rtx, rtx))
 {
-  machine_mode inner = GET_MODE_INNER (mode);
-  unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner);
+  unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_UNIT_SIZE (mode);
   rtx tmpsum = op1;
 
   for (i = parts / 2; i >= 1; i /= 2)
@@ -12918,10 +12915,7 @@ neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
 HOST_WIDE_INT
 neon_element_bits (machine_mode mode)
 {
-  if (mode == DImode)
-    return GET_MODE_BITSIZE (mode);
-  else
-    return GET_MODE_BITSIZE (GET_MODE_INNER (mode));
+  return GET_MODE_UNIT_BITSIZE (mode);
 }
 
 
@@ -22436,7 +22430,7 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
       gcc_assert (GET_CODE (x) == CONST_VECTOR);
 
       units = CONST_VECTOR_NUNITS (x);
-      size = GET_MODE_SIZE (GET_MODE_INNER (mode));
+      size = GET_MODE_UNIT_SIZE (mode);
 
       if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
         for (i = 0; i < units; i++)
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index c1ccad17bf0..e5a2b0f1c9a 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2672,12 +2672,12 @@
 	 to this model.  */
       unsigned int elt = INTVAL (operands[2]);
       unsigned int reg_nelts
-	= 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode));
+	= 64 / GET_MODE_UNIT_BITSIZE (<MODE>mode);
       elt ^= reg_nelts - 1;
       operands[2] = GEN_INT (elt);
     }
 
-  if (GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode)) == 32)
+  if (GET_MODE_UNIT_BITSIZE (<MODE>mode) == 32)
     emit_insn (gen_vec_extract<mode> (operands[0], operands[1], operands[2]));
   else
     emit_insn (gen_neon_vget_lane<mode>_sext_internal (operands[0],
@@ -2701,12 +2701,12 @@
 	 to this model.  */
       unsigned int elt = INTVAL (operands[2]);
       unsigned int reg_nelts
-	= 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode));
+	= 64 / GET_MODE_UNIT_BITSIZE (<MODE>mode);
       elt ^= reg_nelts - 1;
       operands[2] = GEN_INT (elt);
     }
 
-  if (GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode)) == 32)
+  if (GET_MODE_UNIT_BITSIZE (<MODE>mode) == 32)
     emit_insn (gen_vec_extract<mode> (operands[0], operands[1], operands[2]));
   else
     emit_insn (gen_neon_vget_lane<mode>_zext_internal (operands[0],
@@ -2766,7 +2766,7 @@ if (BYTES_BIG_ENDIAN)
   if (BYTES_BIG_ENDIAN)
     {
       unsigned int reg_nelts
-	= 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode));
+	= 64 / GET_MODE_UNIT_BITSIZE (<MODE>mode);
       elt ^= reg_nelts - 1;
     }
 
@@ -2869,7 +2869,7 @@ if (BYTES_BIG_ENDIAN)
     {
       unsigned int elt = INTVAL (operands[2]);
       unsigned int reg_nelts
-	= 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<V_double_vector_mode>mode));
+	= 64 / GET_MODE_UNIT_BITSIZE (<V_double_vector_mode>mode);
       elt ^= reg_nelts - 1;
       operands[2] = GEN_INT (elt);
     }
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 682c5073857..a48e8c5331d 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -6986,7 +6986,7 @@ classify_argument (machine_mode mode, const_tree type,
 
   /* for V1xx modes, just use the base mode */
   if (VECTOR_MODE_P (mode) && mode != V1DImode && mode != V1TImode
-      && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
+      && GET_MODE_UNIT_SIZE (mode) == bytes)
     mode = GET_MODE_INNER (mode);
 
   /* Classification of atomic types.  */
@@ -13167,7 +13167,7 @@ ix86_legitimate_constant_p (machine_mode, rtx x)
 #endif
       break;
 
-    case CONST_DOUBLE:
+    case CONST_WIDE_INT:
       if (GET_MODE (x) == TImode
 	  && x != CONST0_RTX (TImode)
           && !TARGET_64BIT)
@@ -13197,6 +13197,7 @@ ix86_cannot_force_const_mem (machine_mode mode, rtx x)
   switch (GET_CODE (x))
     {
     case CONST_INT:
+    case CONST_WIDE_INT:
     case CONST_DOUBLE:
     case CONST_VECTOR:
       return false;
@@ -13223,7 +13224,7 @@ is_imported_p (rtx x)
 
 /* Nonzero if the constant value X is a legitimate general operand
    when generating PIC code.  It is given that flag_pic is on and
-   that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
+   that X satisfies CONSTANT_P.  */
 
 bool
 legitimate_pic_operand_p (rtx x)
@@ -14749,20 +14750,9 @@ output_pic_addr_const (FILE *file, rtx x, int code)
       break;
 
     case CONST_DOUBLE:
-      if (GET_MODE (x) == VOIDmode)
-	{
-	  /* We can use %d if the number is <32 bits and positive.  */
-	  if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
-	    fprintf (file, "0x%lx%08lx",
-		     (unsigned long) CONST_DOUBLE_HIGH (x),
-		     (unsigned long) CONST_DOUBLE_LOW (x));
-	  else
-	    fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
-	}
-      else
-	/* We can't handle floating point constants;
-	   TARGET_PRINT_OPERAND must handle them.  */
-	output_operand_lossage ("floating constant misused");
+      /* We can't handle floating point constants;
+	 TARGET_PRINT_OPERAND must handle them.  */
+      output_operand_lossage ("floating constant misused");
       break;
 
     case PLUS:
@@ -15122,8 +15112,7 @@ ix86_find_base_term (rtx x)
 	return x;
       term = XEXP (x, 0);
       if (GET_CODE (term) == PLUS
-	  && (CONST_INT_P (XEXP (term, 1))
-	      || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
+	  && CONST_INT_P (XEXP (term, 1)))
 	term = XEXP (term, 0);
       if (GET_CODE (term) != UNSPEC
 	  || (XINT (term, 1) != UNSPEC_GOTPCREL
@@ -16136,7 +16125,7 @@ ix86_print_operand (FILE *file, rtx x, int code)
 
       if (code != 'P' && code != 'p')
 	{
-	  if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
+	  if (CONST_INT_P (x))
 	    {
 	      if (ASSEMBLER_DIALECT == ASM_ATT)
 		putc ('$', file);
@@ -19625,12 +19614,9 @@ rtx
 ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert)
 {
   machine_mode vec_mode, imode;
-  HOST_WIDE_INT hi, lo;
-  int shift = 63;
-  rtx v;
-  rtx mask;
+  wide_int w;
+  rtx mask, v;
 
-  /* Find the sign bit, sign extended to 2*HWI.  */
   switch (mode)
     {
     case V16SImode:
@@ -19640,9 +19626,7 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert)
     case V8SFmode:
     case V4SFmode:
       vec_mode = mode;
-      mode = GET_MODE_INNER (mode);
       imode = SImode;
-      lo = 0x80000000, hi = lo < 0;
       break;
 
     case V8DImode:
@@ -19652,60 +19636,31 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert)
     case V4DFmode:
     case V2DFmode:
       vec_mode = mode;
-      mode = GET_MODE_INNER (mode);
       imode = DImode;
-      if (HOST_BITS_PER_WIDE_INT >= 64)
-	lo = (HOST_WIDE_INT)1 << shift, hi = -1;
-      else
-	lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
       break;
 
     case TImode:
     case TFmode:
       vec_mode = VOIDmode;
-      if (HOST_BITS_PER_WIDE_INT >= 64)
-	{
-	  imode = TImode;
-	  lo = 0, hi = (HOST_WIDE_INT)1 << shift;
-	}
-      else
-	{
-	  rtvec vec;
-
-	  imode = DImode;
-	  lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
-
-	  if (invert)
-	    {
-	      lo = ~lo, hi = ~hi;
-	      v = constm1_rtx;
-	    }
-	  else
-	    v = const0_rtx;
-
-	  mask = immed_double_const (lo, hi, imode);
-
-	  vec = gen_rtvec (2, v, mask);
-	  v = gen_rtx_CONST_VECTOR (V2DImode, vec);
-	  v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
-
-	  return v;
-	}
-     break;
+      imode = TImode;
+      break;
 
     default:
       gcc_unreachable ();
     }
 
+  machine_mode inner_mode = GET_MODE_INNER (mode);
+  w = wi::set_bit_in_zero (GET_MODE_BITSIZE (inner_mode) - 1,
+			   GET_MODE_BITSIZE (inner_mode));
   if (invert)
-    lo = ~lo, hi = ~hi;
+    w = wi::bit_not (w);
 
   /* Force this value into the low part of a fp vector constant.  */
-  mask = immed_double_const (lo, hi, imode);
-  mask = gen_lowpart (mode, mask);
+  mask = immed_wide_int_const (w, imode);
+  mask = gen_lowpart (inner_mode, mask);
 
   if (vec_mode == VOIDmode)
-    return force_reg (mode, mask);
+    return force_reg (inner_mode, mask);
 
   v = ix86_build_const_vector (vec_mode, vect, mask);
   return force_reg (vec_mode, v);
@@ -21852,13 +21807,13 @@ ix86_expand_int_vcond (rtx operands[])
       && data_mode == mode
       && cop1 == CONST0_RTX (mode)
       && operands[1 + (code == LT)] == CONST0_RTX (data_mode)
-      && GET_MODE_SIZE (GET_MODE_INNER (data_mode)) > 1
-      && GET_MODE_SIZE (GET_MODE_INNER (data_mode)) <= 8
+      && GET_MODE_UNIT_SIZE (data_mode) > 1
+      && GET_MODE_UNIT_SIZE (data_mode) <= 8
       && (GET_MODE_SIZE (data_mode) == 16
 	  || (TARGET_AVX2 && GET_MODE_SIZE (data_mode) == 32)))
     {
       rtx negop = operands[2 - (code == LT)];
-      int shift = GET_MODE_BITSIZE (GET_MODE_INNER (data_mode)) - 1;
+      int shift = GET_MODE_UNIT_BITSIZE (data_mode) - 1;
       if (negop == CONST1_RTX (data_mode))
 	{
 	  rtx res = expand_simple_binop (mode, LSHIFTRT, cop0, GEN_INT (shift),
@@ -22916,26 +22871,21 @@ ix86_split_to_parts (rtx operand, rtx *parts, machine_mode mode)
 	      REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
 	      real_to_target (l, &r, mode);
 
-	      /* Do not use shift by 32 to avoid warning on 32bit systems.  */
-	      if (HOST_BITS_PER_WIDE_INT >= 64)
-	        parts[0]
-		  = gen_int_mode
-		      ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
-		       + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
-		       DImode);
-	      else
-	        parts[0] = immed_double_const (l[0], l[1], DImode);
+	      /* real_to_target puts 32-bit pieces in each long.  */
+	      parts[0] =
+		gen_int_mode
+		  ((l[0] & (HOST_WIDE_INT) 0xffffffff)
+		   | ((l[1] & (HOST_WIDE_INT) 0xffffffff) << 32),
+		   DImode);
 
 	      if (upper_mode == SImode)
 	        parts[1] = gen_int_mode (l[2], SImode);
-	      else if (HOST_BITS_PER_WIDE_INT >= 64)
-	        parts[1]
-		  = gen_int_mode
-		      ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
-		       + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
-		       DImode);
 	      else
-	        parts[1] = immed_double_const (l[2], l[3], DImode);
+	        parts[1] =
+		  gen_int_mode
+		    ((l[2] & (HOST_WIDE_INT) 0xffffffff)
+		     | ((l[3] & (HOST_WIDE_INT) 0xffffffff) << 32),
+		     DImode);
 	    }
 	  else
 	    gcc_unreachable ();
@@ -36222,7 +36172,7 @@ ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
 		xop_rotl:
 		  if (CONST_INT_P (op))
 		    {
-		      int mask = GET_MODE_BITSIZE (GET_MODE_INNER (tmode)) - 1;
+		      int mask = GET_MODE_UNIT_BITSIZE (tmode) - 1;
 		      op = GEN_INT (INTVAL (op) & mask);
 		      gcc_checking_assert
 			(insn_data[icode].operand[i + 1].predicate (op, mode));
@@ -42274,12 +42224,11 @@ ix86_rtx_costs (rtx x, int code_i, int outer_code_i, int opno, int *total,
 	*total = 0;
       return true;
 
+    case CONST_WIDE_INT:
+      *total = 0;
+      return true;
+
     case CONST_DOUBLE:
-      if (mode == VOIDmode)
-	{
-	  *total = 0;
-	  return true;
-	}
       switch (standard_80387_constant_p (x))
 	{
 	case 1: /* 0.0 */
@@ -45622,12 +45571,12 @@ ix86_expand_reduc (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
     }
 
   for (i = GET_MODE_BITSIZE (mode);
-       i > GET_MODE_BITSIZE (GET_MODE_INNER (mode));
+       i > GET_MODE_UNIT_BITSIZE (mode);
        i >>= 1)
     {
       half = gen_reg_rtx (mode);
       emit_reduc_half (half, vec, i);
-      if (i == GET_MODE_BITSIZE (GET_MODE_INNER (mode)) * 2)
+      if (i == GET_MODE_UNIT_BITSIZE (mode) * 2)
 	dst = dest;
       else
 	dst = gen_reg_rtx (mode);
@@ -47068,7 +47017,7 @@ expand_vec_perm_blend (struct expand_vec_perm_d *d)
     return false;
   if (TARGET_AVX512F && GET_MODE_SIZE (vmode) == 64
       && (TARGET_AVX512BW
-	  || GET_MODE_SIZE (GET_MODE_INNER (vmode)) >= 4))
+	  || GET_MODE_UNIT_SIZE (vmode) >= 4))
     ;
   else if (TARGET_AVX2 && GET_MODE_SIZE (vmode) == 32)
     ;
@@ -47515,7 +47464,7 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d)
       rperm[i] = GEN_INT ((d->perm[i * nelt / 16] * 16 / nelt) & 15);
   else
     {
-      eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
+      eltsz = GET_MODE_UNIT_SIZE (d->vmode);
       if (!d->one_operand_p)
 	mask = 2 * nelt - 1;
       else if (vmode == V16QImode)
@@ -47887,7 +47836,7 @@ expand_vec_perm_palignr (struct expand_vec_perm_d *d, bool single_insn_only_p)
       return expand_vec_perm_1 (&dcopy);
     }
 
-  shift = GEN_INT (min * GET_MODE_BITSIZE (GET_MODE_INNER (d->vmode)));
+  shift = GEN_INT (min * GET_MODE_UNIT_BITSIZE (d->vmode));
   if (GET_MODE_SIZE (d->vmode) == 16)
     {
       target = gen_reg_rtx (TImode);
@@ -48692,7 +48641,7 @@ expand_vec_perm_pshufb2 (struct expand_vec_perm_d *d)
     return true;
 
   nelt = d->nelt;
-  eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
+  eltsz = GET_MODE_UNIT_SIZE (d->vmode);
 
   /* Generate two permutation masks.  If the required element is within
      the given vector it is shuffled into the proper lane.  If the required
@@ -48756,7 +48705,7 @@ expand_vec_perm_vpshufb2_vpermq (struct expand_vec_perm_d *d)
     return true;
 
   nelt = d->nelt;
-  eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
+  eltsz = GET_MODE_UNIT_SIZE (d->vmode);
 
   /* Generate two permutation masks.  If the required element is within
      the same lane, it is shuffled in.  If the required element from the
@@ -48832,7 +48781,7 @@ expand_vec_perm_vpshufb2_vpermq_even_odd (struct expand_vec_perm_d *d)
     return true;
 
   nelt = d->nelt;
-  eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
+  eltsz = GET_MODE_UNIT_SIZE (d->vmode);
 
   /* Generate two permutation masks.  In the first permutation mask
      the first quarter will contain indexes for the first half
@@ -49483,7 +49432,7 @@ expand_vec_perm_vpshufb4_vpermq2 (struct expand_vec_perm_d *d)
     return true;
 
   nelt = d->nelt;
-  eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
+  eltsz = GET_MODE_UNIT_SIZE (d->vmode);
 
   /* Generate 4 permutation masks.  If the required element is within
      the same lane, it is shuffled in.  If the required element from the
@@ -50400,8 +50349,7 @@ ix86_expand_sse2_abs (rtx target, rtx input)
 	 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)).  */
       case V4SImode:
 	tmp0 = expand_simple_binop (mode, ASHIFTRT, input,
-				    GEN_INT (GET_MODE_BITSIZE
-					     (GET_MODE_INNER (mode)) - 1),
+				    GEN_INT (GET_MODE_UNIT_BITSIZE (mode) - 1),
 				    NULL, 0, OPTAB_DIRECT);
 	tmp1 = expand_simple_binop (mode, XOR, tmp0, input,
 				    NULL, 0, OPTAB_DIRECT);
@@ -50989,6 +50937,7 @@ find_constant (rtx in_rtx, imm_info *imm_values)
 	  break;
 
 	case CONST_DOUBLE:
+	case CONST_WIDE_INT:
 	  (imm_values->imm)++;
 	  (imm_values->imm64)++;
 	  break;
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 9637ce3e9ae..9f48b187143 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2571,6 +2571,8 @@ extern void debug_dispatch_window (int);
 /* For switching between functions with different target attributes.  */
 #define SWITCHABLE_TARGET 1
 
+#define TARGET_SUPPORTS_WIDE_INT 1
+
 /*
 Local variables:
 version-control: t
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index e0ab116af74..345333b72a1 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10748,17 +10748,10 @@
   "TARGET_64BIT && !TARGET_USE_BT"
   [(const_int 0)]
 {
-  HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
-  rtx op1;
+  int i = INTVAL (operands[1]);
 
-  if (HOST_BITS_PER_WIDE_INT >= 64)
-    lo = (HOST_WIDE_INT)1 << i, hi = 0;
-  else if (i < HOST_BITS_PER_WIDE_INT)
-    lo = (HOST_WIDE_INT)1 << i, hi = 0;
-  else
-    lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
+  rtx op1 = gen_int_mode (HOST_WIDE_INT_1U << i, DImode);
 
-  op1 = immed_double_const (lo, hi, DImode);
   if (i >= 31)
     {
       emit_move_insn (operands[2], op1);
@@ -10780,17 +10773,10 @@
   "TARGET_64BIT && !TARGET_USE_BT"
   [(const_int 0)]
 {
-  HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
-  rtx op1;
-
-  if (HOST_BITS_PER_WIDE_INT >= 64)
-    lo = (HOST_WIDE_INT)1 << i, hi = 0;
-  else if (i < HOST_BITS_PER_WIDE_INT)
-    lo = (HOST_WIDE_INT)1 << i, hi = 0;
-  else
-    lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
+  int i = INTVAL (operands[1]);
 
-  op1 = immed_double_const (~lo, ~hi, DImode);
+  rtx op1 = gen_int_mode (HOST_WIDE_INT_1U << i, DImode);
+ 
   if (i >= 32)
     {
       emit_move_insn (operands[2], op1);
@@ -10813,17 +10799,10 @@
   "TARGET_64BIT && !TARGET_USE_BT"
   [(const_int 0)]
 {
-  HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
-  rtx op1;
+  int i = INTVAL (operands[1]);
 
-  if (HOST_BITS_PER_WIDE_INT >= 64)
-    lo = (HOST_WIDE_INT)1 << i, hi = 0;
-  else if (i < HOST_BITS_PER_WIDE_INT)
-    lo = (HOST_WIDE_INT)1 << i, hi = 0;
-  else
-    lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
+  rtx op1 = gen_int_mode (HOST_WIDE_INT_1U << i, DImode);
 
-  op1 = immed_double_const (lo, hi, DImode);
   if (i >= 31)
     {
       emit_move_insn (operands[2], op1);
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index f0c999cb182..478b8f0a83a 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -144,18 +144,10 @@
   switch (GET_CODE (op))
     {
     case CONST_INT:
-      /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
-         to be at least 32 and this all acceptable constants are
-	 represented as CONST_INT.  */
-      if (HOST_BITS_PER_WIDE_INT == 32)
-	return true;
-      else
-	{
-	  HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
-	  return trunc_int_for_mode (val, SImode) == val;
-	}
-      break;
-
+      {
+        HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
+        return trunc_int_for_mode (val, SImode) == val;
+      }
     case SYMBOL_REF:
       /* For certain code models, the symbolic references are known to fit.
 	 in CM_SMALL_PIC model we know it fits if it is local to the shared
@@ -262,21 +254,12 @@
 
 ;; Return true if VALUE can be stored in the zero extended immediate field.
 (define_predicate "x86_64_zext_immediate_operand"
-  (match_code "const_double,const_int,symbol_ref,label_ref,const")
+  (match_code "const_int,symbol_ref,label_ref,const")
 {
   switch (GET_CODE (op))
     {
-    case CONST_DOUBLE:
-      if (HOST_BITS_PER_WIDE_INT == 32)
-	return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
-      else
-	return false;
-
     case CONST_INT:
-      if (HOST_BITS_PER_WIDE_INT == 32)
-	return INTVAL (op) >= 0;
-      else
-	return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
+      return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
 
     case SYMBOL_REF:
       /* For certain code models, the symbolic references are known to fit.  */
@@ -629,7 +612,7 @@
 
 ;; Match exactly zero.
 (define_predicate "const0_operand"
-  (match_code "const_int,const_double,const_vector")
+  (match_code "const_int,const_wide_int,const_double,const_vector")
 {
   if (mode == VOIDmode)
     mode = GET_MODE (op);
@@ -638,7 +621,7 @@
 
 ;; Match -1.
 (define_predicate "constm1_operand"
-  (match_code "const_int,const_double,const_vector")
+  (match_code "const_int,const_wide_int,const_double,const_vector")
 {
   if (mode == VOIDmode)
     mode = GET_MODE (op);
@@ -647,7 +630,7 @@
 
 ;; Match one or vector filled with ones.
 (define_predicate "const1_operand"
-  (match_code "const_int,const_double,const_vector")
+  (match_code "const_int,const_wide_int,const_double,const_vector")
 {
   if (mode == VOIDmode)
     mode = GET_MODE (op);
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index dc7f6a7bab0..8bd3352a553 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -11782,7 +11782,7 @@
 {
   int mask,selector;
   mask = INTVAL (operands[3]);
-  selector = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 4 ?
+  selector = GET_MODE_UNIT_SIZE (<MODE>mode) == 4 ?
     0xFFFF ^ (0xF000 >> mask * 4)
     : 0xFF ^ (0xC0 >> mask * 2);
   emit_insn (gen_<extract_type>_vinsert<shuffletype><extract_suf>_1_mask
@@ -17556,8 +17556,8 @@
 	  [(match_operand 3 "const_int_operand" "n, n")])))]
   "TARGET_SSSE3"
 {
-  machine_mode imode = GET_MODE_INNER (GET_MODE (operands[0]));
-  operands[2] = GEN_INT (INTVAL (operands[3]) * GET_MODE_SIZE (imode));
+  operands[2] =
+   GEN_INT (INTVAL (operands[3]) * GET_MODE_UNIT_SIZE (GET_MODE (operands[0])));
 
   switch (which_alternative)
     {
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index bb7f45d25e7..d06e9a8d48e 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -31740,8 +31740,7 @@ rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
   imode = vmode;
   if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT)
     {
-      imode = GET_MODE_INNER (vmode);
-      imode = mode_for_size (GET_MODE_BITSIZE (imode), MODE_INT, 0);
+      imode = mode_for_size (GET_MODE_UNIT_BITSIZE (vmode), MODE_INT, 0);
       imode = mode_for_vector (imode, nelt);
     }
 
@@ -31810,7 +31809,7 @@ rs6000_complex_function_value (machine_mode mode)
   unsigned int regno;
   rtx r1, r2;
   machine_mode inner = GET_MODE_INNER (mode);
-  unsigned int inner_bytes = GET_MODE_SIZE (inner);
+  unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
 
   if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
     regno = FP_ARG_RETURN;
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index e99cea37d05..3ad9035a884 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -3415,11 +3415,8 @@ arith_immediate_p (rtx op, machine_mode mode,
 
   constant_to_array (mode, op, arr);
 
-  if (VECTOR_MODE_P (mode))
-    mode = GET_MODE_INNER (mode);
-
-  bytes = GET_MODE_SIZE (mode);
-  mode = mode_for_size (GET_MODE_BITSIZE (mode), MODE_INT, 0);
+  bytes = GET_MODE_UNIT_SIZE (mode);
+  mode = mode_for_size (GET_MODE_UNIT_BITSIZE (mode), MODE_INT, 0);
 
   /* Check that bytes are repeated. */
   for (i = bytes; i < 16; i += bytes)
@@ -3459,8 +3456,7 @@ exp2_immediate_p (rtx op, machine_mode mode, int low, int high)
 
   constant_to_array (mode, op, arr);
 
-  if (VECTOR_MODE_P (mode))
-    mode = GET_MODE_INNER (mode);
+  mode = GET_MODE_INNER (mode);
 
   bytes = GET_MODE_SIZE (mode);
   int_mode = mode_for_size (GET_MODE_BITSIZE (mode), MODE_INT, 0);