diff options
| author | tnfchris <tnfchris@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-06-07 09:36:17 +0000 |
|---|---|---|
| committer | tnfchris <tnfchris@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-06-07 09:36:17 +0000 |
| commit | a5e542cb0f17dc955aa2886cf378f8f68389f60b (patch) | |
| tree | f28b8a859a784c1b44d7d836c9cb85ba5ffddd7b /gcc/config | |
| parent | 48a582eb0e899582ed63b029270370e674017d61 (diff) | |
| download | gcc-a5e542cb0f17dc955aa2886cf378f8f68389f60b.tar.gz | |
2017-06-07 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.md
(copysignsf3): Fix mask generation.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248949 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index d89df66fecc..2e9331fd72b 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4973,14 +4973,16 @@ (match_operand:SF 2 "register_operand")] "TARGET_FLOAT && TARGET_SIMD" { - rtx mask = gen_reg_rtx (DImode); + rtx v_bitmask = gen_reg_rtx (V2SImode); /* Juggle modes to get us in to a vector mode for BSL. */ - rtx op1 = lowpart_subreg (V2SFmode, operands[1], SFmode); + rtx op1 = lowpart_subreg (DImode, operands[1], SFmode); rtx op2 = lowpart_subreg (V2SFmode, operands[2], SFmode); rtx tmp = gen_reg_rtx (V2SFmode); - emit_move_insn (mask, GEN_INT (HOST_WIDE_INT_1U << 31)); - emit_insn (gen_aarch64_simd_bslv2sf (tmp, mask, op2, op1)); + emit_move_insn (v_bitmask, + aarch64_simd_gen_const_vector_dup (V2SImode, + HOST_WIDE_INT_M1U << 31)); + emit_insn (gen_aarch64_simd_bslv2sf (tmp, v_bitmask, op2, op1)); emit_move_insn (operands[0], lowpart_subreg (SFmode, tmp, V2SFmode)); DONE; } |