diff options
| author | mrs <mrs@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-10-30 03:02:00 +0000 |
|---|---|---|
| committer | mrs <mrs@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-10-30 03:02:00 +0000 |
| commit | 0d58d930a74fccc0321215f32050bf71c21e3c28 (patch) | |
| tree | 3e4d8c33a6e93f29e60f5b1a8bb6ff6874206439 /gcc/config | |
| parent | 74e1763b12ef3120de576e4058229c0d3acb5f8e (diff) | |
| download | gcc-0d58d930a74fccc0321215f32050bf71c21e3c28.tar.gz | |
* machmode.def (PARTIAL_INT_MODE): Add precision and name.
* genmodes.c (PARTIAL_INT_MODE): Add precision and name.
(make_vector_mode): Increase namebuf to 16.
(emit_insn_modes_h): When processing BImode, don't
also match partial int modes.
(emit_class_narrowest_mode): Likewise.
* config/bfin/bfin-modes.def: Add precision to PDI.
* config/m32c/m32c-modes.def: Add precision to PSI.
* config/msp430/msp430-modes.def: Add precision to PSI.
* config/rs6000/rs6000-modes.def: Add precision to PTI.
* config/sh/sh-modes.def: Add precision to PSI and PDI.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@204193 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/bfin/bfin-modes.def | 2 | ||||
| -rw-r--r-- | gcc/config/m32c/m32c-modes.def | 2 | ||||
| -rw-r--r-- | gcc/config/msp430/msp430-modes.def | 2 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000-modes.def | 2 | ||||
| -rw-r--r-- | gcc/config/sh/sh-modes.def | 4 |
5 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/bfin/bfin-modes.def b/gcc/config/bfin/bfin-modes.def index cf03a1a7e0d..da0303c8446 100644 --- a/gcc/config/bfin/bfin-modes.def +++ b/gcc/config/bfin/bfin-modes.def @@ -19,7 +19,7 @@ <http://www.gnu.org/licenses/>. */ /* PDImode for the 40-bit accumulators. */ -PARTIAL_INT_MODE (DI); +PARTIAL_INT_MODE (DI, 40, PDI); /* Two of those - covering both accumulators for vector multiplications. */ VECTOR_MODE (INT, PDI, 2); diff --git a/gcc/config/m32c/m32c-modes.def b/gcc/config/m32c/m32c-modes.def index 2050c91a009..ad266fbc851 100644 --- a/gcc/config/m32c/m32c-modes.def +++ b/gcc/config/m32c/m32c-modes.def @@ -22,7 +22,7 @@ /*INT_MODE (PI, 3);*/ /* 24-bit pointers, in 32-bit units */ -PARTIAL_INT_MODE (SI); +PARTIAL_INT_MODE (SI, 24, PSI); /* 48-bit MULEX result */ /* INT_MODE (MI, 6); */ diff --git a/gcc/config/msp430/msp430-modes.def b/gcc/config/msp430/msp430-modes.def index 9e7b70127fd..4e94a6df597 100644 --- a/gcc/config/msp430/msp430-modes.def +++ b/gcc/config/msp430/msp430-modes.def @@ -1,3 +1,3 @@ /* 20-bit address */ -PARTIAL_INT_MODE (SI); +PARTIAL_INT_MODE (SI, 20, PSI); diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index 5124e1665d4..a77aa26e850 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -45,4 +45,4 @@ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ /* Replacement for TImode that only is allowed in GPRs. We also use PTImode for quad memory atomic operations to force getting an even/odd register combination. */ -PARTIAL_INT_MODE (TI); +PARTIAL_INT_MODE (TI, 128, PTI); diff --git a/gcc/config/sh/sh-modes.def b/gcc/config/sh/sh-modes.def index aec007986ef..aa56038d614 100644 --- a/gcc/config/sh/sh-modes.def +++ b/gcc/config/sh/sh-modes.def @@ -18,9 +18,9 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ /* The SH uses a partial integer mode to represent the FPSCR register. */ -PARTIAL_INT_MODE (SI); +PARTIAL_INT_MODE (SI, 22, PSI); /* PDI mode is used to represent a function address in a target register. */ -PARTIAL_INT_MODE (DI); +PARTIAL_INT_MODE (DI, 64, PDI); /* Vector modes. */ VECTOR_MODE (INT, QI, 2); /* V2QI */ |