diff options
| author | vmakarov <vmakarov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-03-29 01:02:05 +0000 |
|---|---|---|
| committer | vmakarov <vmakarov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-03-29 01:02:05 +0000 |
| commit | 66d9a7b9e8a0c85a51467330f51ead74e77b7eb8 (patch) | |
| tree | 42d3a5950c6b4d878e9c4c7bf2af916fdcf79515 /gcc/config | |
| parent | 9f50fa3742ab7c20e3e8ceb48b26c920b22ecd62 (diff) | |
| download | gcc-66d9a7b9e8a0c85a51467330f51ead74e77b7eb8.tar.gz | |
2011-03-28 Vladimir Makarov <vmakarov@redhat.com>
* ira-color.c (update_left_conflict_sizes_p): Don't assume that
conflict object hard regset nodes have intersecting hard reg sets.
* regmove.c (regmove_optimize): Move ira_set_pseudo_classes call
after regstat_init_n_sets_and_refs.
* ira.c: Add more comments at the top.
(setup_stack_reg_pressure_class, setup_pressure_classes):
Add comments how we compute the register pressure classes.
(setup_allocno_and_important_classes): Add more comments.
(setup_class_translate_array, reorder_important_classes)
(setup_reg_class_relations): Add comments.
* ira-emit.c: Add 2011 to the Copyright line. Add comments at the
start of the file.
* ira-color.c: Add 2011 to the Copyright line.
(assign_hard_reg): Add more comments.
(improve_allocation): Ditto.
* ira-costs.c: Add 2011 to the Copyright line.
(setup_cost_classes, setup_regno_cost_classes_by_aclass): Add more
comments.
(setup_regno_cost_classes_by_mode): Ditto.
Initial patches from ira-improv branch:
2010-08-13 Vladimir Makarov <vmakarov@redhat.com>
* ira-build.c: (ira_create_object): Remove initialization of
OBJECT_PROFITABLE_HARD_REGS. Initialize OBJECT_ADD_DATA.
(ira_create_allocno): Remove initialization of
ALLOCNO_MEM_OPTIMIZED_DEST, ALLOCNO_MEM_OPTIMIZED_DEST_P,
ALLOCNO_SOMEWHERE_RENAMED_P, ALLOCNO_CHILD_RENAMED_P,
ALLOCNO_IN_GRAPH_P, ALLOCNO_MAY_BE_SPILLED_P, ALLOCNO_COLORABLE_P,
ALLOCNO_NEXT_BUCKET_ALLOCNO, ALLOCNO_PREV_BUCKET_ALLOCNO,
ALLOCNO_FIRST_COALESCED_ALLOCNO, ALLOCNO_NEXT_COALESCED_ALLOCNO.
Initialize ALLOCNO_ADD_DATA.
(copy_info_to_removed_store_destinations): Use ALLOCNO_EMIT_DATA
and allocno_emit_reg instead of ALLOCNO_MEM_OPTIMIZED_DEST_P and
ALLOCNO_REG.
(ira_flattening): Ditto. Use ALLOCNO_EMIT_DATA instead of
ALLOCNO_MEM_OPTIMIZED_DEST and ALLOCNO_SOMEWHERE_RENAMED_P.
* ira.c (ira_reallocate): Remove.
(setup_pressure_classes): Call
ira_init_register_move_cost_if_necessary. Use
ira_register_move_cost instead of ira_get_register_move_cost.
(setup_allocno_assignment_flags): Use ALLOCNO_EMIT_DATA.
(ira): Call ira_initiate_emit_data and ira_finish_emit_data.
* ira-color.c: Use ALLOCNO_COLOR_DATA instead of
ALLOCNO_IN_GRAPH_P, ALLOCNO_MAY_BE_SPILLED_P, ALLOCNO_COLORABLE_P,
ALLOCNO_AVAILABLE_REGS_NUM, ALLOCNO_NEXT_BUCKET_ALLOCNO,
ALLOCNO_PREV_BUCKET_ALLOCNO. ALLOCNO_TEMP. Use OBJECT_COLOR_DATA
instead of OBJECT_PROFITABLE_HARD_REGS, OBJECT_HARD_REGS_NODE,
OBJECT_HARD_REGS_SUBNODES_START, OBJECT_HARD_REGS_SUBNODES_NUM.
Fix formatting.
(object_hard_regs_t, object_hard_regs_node_t): Move from
ira-int.h.
(struct object_hard_regs, struct object_hard_regs_node): Ditto.
(struct allocno_color_data): New.
(allocno_color_data_t): New typedef.
(allocno_color_data): New definition.
(ALLOCNO_COLOR_DATA): New macro.
(struct object_color_data): New.
(object_color_data_t): New typedef.
(object_color_data): New definition.
(OBJECT_COLOR_DATA): New macro.
(update_copy_costs, calculate_allocno_spill_cost): Call
ira_init_register_move_cost_if_necessary. Use
ira_register_move_cost instead of ira_get_register_move_cost.
(move_spill_restore, update_curr_costs): Ditto.
(allocno_spill_priority): Make it inline.
(color_pass): Allocate and free allocno_color_dat and
object_color_data.
(struct coalesce_data, coalesce_data_t): New.
(allocno_coalesce_data): New definition.
(ALLOCNO_COALESCE_DATA): New macro.
(merge_allocnos, coalesced_allocno_conflict_p): Use
ALLOCNO_COALESCED_DATA instead of ALLOCNO_FIRST_COALESCED_ALLOCNO,
ALLOCNO_NEXT_COALESCED_ALLOCNO, ALLOCNO_TEMP.
(coalesce_allocnos): Ditto.
(setup_coalesced_allocno_costs_and_nums): Ditto.
(collect_spilled_coalesced_allocnos): Ditto.
(slot_coalesced_allocno_live_ranges_intersect_p): Ditto.
(setup_slot_coalesced_allocno_live_ranges): Ditto.
(coalesce_spill_slots): Ditto.
(ira_sort_regnos_for_alter_reg): Ditto. Allocate, initialize and
free allocno_coalesce_data.
* ira-conflicts.c: Fix formatting.
(process_regs_for_copy): Call
ira_init_register_move_cost_if_necessary. Use
ira_register_move_cost instead of ira_get_register_move_cost.
(build_object_conflicts): Optimize.
* ira-costs.c (record_reg_classes): Optimize. Call
ira_init_register_move_cost_if_necessary. Use
ira_register_move_cost, ira_may_move_in_cost, and
ira_may_move_out_cost instead of ira_get_register_move_cost and
ira_get_may_move_cost.
(record_address_regs): Ditto.
(scan_one_insn): Optimize.
(find_costs_and_classes): Optimize.
(process_bb_node_for_hard_reg_moves): Call
ira_init_register_move_cost_if_necessary. Use
ira_register_move_cost instead of ira_get_register_move_cost.
* ira-emit.c: Use allocno_emit_reg, ALLOCNO_EMIT_DATA instead of
ALLOCNO_REG, ALLOCNO_CHILD_RENAMED_P, ALLOCNO_MEM_OPTIMIZED_DEST,
ALLOCNO_MEM_OPTIMIZED_DEST_P, and ALLOCNO_SOMEWHERE_RENAMED_P.
(ira_allocno_emit_data, void_p, new_allocno_emit_data_vec): New
definitions.
(ira_initiate_emit_data, ira_finish_emit_data)
(create_new_allocno): New functions.
(modify_move_list): Call create_new_alloc instead of
ira_create_allocno.
(emit_move_list): Call ira_init_register_move_cost_if_necessary.
Use ira_register_move_cost instead of ira_get_register_move_cost.
* ira-int.h: Fix some comments.
(object_hard_regs_t, object_hard_regs_node_t): Move
to ira-color.c.
(struct object_hard_regs, struct object_hard_regs_node):
Ditto.
(struct ira_object): Remove profitable_hard_regs, hard_regs_node,
hard_regs_subnodes_start, hard_regs_subnodes_num. Add new member
add_data.
(struct ira_allocno): Make mode and aclass a bitfield. Move other
bitfield after mode. Make hard_regno a short int. Make
hard_regno short. Remove first_coalesced_allocno and
next_coalesced_allocno. Move mem_optimized_dest_p,
somewhere_renamed_p, child_renamed_p, reg, and mem_optimized_dest
into struct ira_emit_data. Remove in_graph_p, may_be_spilled_p,
available_regs_num, next_bucket_allocno, prev_bucket_allocno,
temp, colorable_p. Add new member add_data.
(ALLOCNO_IN_GRAPH_P, ALLOCNO_MAY_BE_SPILLED_P): Remove.
(ALLOCNO_COLORABLE_P, ALLOCNO_AVAILABLE_REGS_NUM): Remove.
(ALLOCNO_NEXT_BUCKET_ALLOCNO, ALLOCNO_PREV_BUCKET_ALLOCNO): Remove.
(ALLOCNO_TEMP, ALLOCNO_FIRST_COALESCED_ALLOCNO): Remove.
(ALLOCNO_NEXT_COALESCED_ALLOCNO): Remove.
(ALLOCNO_ADD_DATA): New macro.
(ira_emit_data_t): New typedef.
(struct ira_emit_data): New. Move mem_optimized_dest_p,
somewhere_renamed_p, child_renamed_p, reg, mem_optimized_dest
from struct ira_allocno.
(ALLOCNO_EMIT_DATA): New macro.
(ira_allocno_emit_data, allocno_emit_reg): New.
(ALLOCNO_PROFITABLE_HARD_REGS, OBJECT_HARD_REGS_NODE): Remove.
(OBJECT_HARD_REGS_SUBNODES_STAR, OBJECT_HARD_REGS_SUBNODES_NUM):
Remove.
(OBJECT_ADD_DATA): New macro.
(ira_reallocate): Remove.
(ira_initiate_emit_data, ira_finish_emit_data): New.
(ira_get_register_move_cost, ira_get_may_move_cost): Remove.
(ira_init_register_move_cost_if_necessary): New.
(ira_object_conflict_iter_next): Merge into
ira_object_conflict_iter_cond.
(FOR_EACH_OBJECT_CONFLICT): Don't use
ira_object_conflict_iter_next.
* ira-live.c: (process_single_reg_class_operands): Call
ira_init_register_move_cost_if_necessary. Use
ira_register_move_cost instead of ira_get_register_move_cost.
2010-08-13 Vladimir Makarov <vmakarov@redhat.com>
* ira-int.h (struct target_ira_int): Remove x_cost_classes.
* ira-costs.c: Fix formatting.
(cost_classes, cost_classes_num): Remove.
(struct cost_classes, cost_classes_t, const_cost_classes_t): New.
(regno_cost_classes, cost_classes_hash, cost_classes_eq): New.
(cost_classes_del, cost_classes_htab): New.
(cost_classes_aclass_cache, cost_classes_mode_cache): New.
(initiate_regno_cost_classes, setup_cost_classes): New.
(setup_regno_cost_classes_by_aclass): New.
(setup_regno_cost_classes_by_mode, finish_regno_cost_classes):
New.
(record_reg_classes): Use regno_cost_classes instead of
cost_classes. Move checking opposite operand up.
(record_address_regs): Use regno_cost_classes
instead of cost_classes.
(scan_one_insn): Ditto. Use always general register.
(print_allocno_costs): Use regno_cost_classes instead of
cost_classes.
(print_pseudo_costs): Ditto. Use Reg_N_REFS.
(find_costs_and_classes): Set up cost classes for each registers.
Use also their mode for this. Use regno_cost_classes instead of
cost_classes.
(setup_allocno_class_and_costs): Use regno_cost_classes instead of
cost_classes.
(free_ira_costs, ira_init_costs): Don't use cost_classes.
(ira_costs, ira_set_pseudo_classes): Call
initiate_regno_cost_classes and finish_regno_cost_classes.
2010-10-04 Vladimir Makarov <vmakarov@redhat.com>
* target-def.h (TARGET_IRA_COVER_CLASSES): Remove.
* target.def (ira_cover_classes): Remove.
* doc/tm.texi: Remove TARGET_IRA_COVER_CLASSES and
IRA_COVER_CLASSES.
* doc/tm.texi.in: Ditto.
* ira-conflicts.c: Remove mentioning cover classes from the file.
Use ALLOCNO_CLASS instead of ALLOCNO_COVER_CLASS. Use
ALLOCNO_COVER_CLASS_COST instead of ALLOCNO_CLASS_COST. Fix
formatting.
* targhooks.c (default_ira_cover_classes): Remove.
* targhooks.h (default_ira_cover_classes): Ditto.
* haifa-sched.c: Remove mentioning cover classes from the file.
Use ira_reg_pressure_cover instead of ira_reg_class_cover. Use
ira_pressure_classes and ira_pressure_classes_num instead of
ira_reg_class_cover_size and ira_reg_class_cover. Use
sched_regno_pressure_class instead of sched_regno_cover_class.
(mark_regno_birth_or_death, setup_insn_reg_pressure_info): Use
ira_reg_class_max_nregs instead of ira_reg_class_nregs.
* ira-int.h: Add 2010 to Copyright. Remove mentioning cover
classes from the file.
(object_hard_regs_t, object_hard_regs_node_t): New typedefs.
(struct object_hard_regs, struct object_hard_regs_node): New.
(struct ira_object): New members profitable_hard_regs,
hard_regs_node, hard_regs_subnodes_start, hard_regs_subnodes_num.
(struct ira_allocno): Rename cover_class to aclass. Rename
cover_class_cost and updated_cover_class_cost to class_cost and
updated_class_cost. Remove splay_removed_p and
left_conflict_size. Add new members colorable_p.
(ALLOCNO_SPLAY_REMOVED_P, ALLOCNO_LEFT_CONFLICTS_SIZE): Remove.
(ALLOCNO_COLORABLE_P): New macro.
(ALLOCNO_COVER_CLASS): Rename to ALLOCNO_CLASS.
(ALLOCNO_COVER_CLASS_COST, ALLOCNO_UPDATED_COVER_CLASS_COST):
Rename to ALLOCNO_CLASS_COST and ALLOCNO_UPDATED__CLASS_COST.
(OBJECT_...): Rename parameter C to O.
(OBJECT_PROFITABLE_HARD_REGS): New macro.
(OBJECT_HARD_REGS_NODE, OBJECT_HARD_REGS_SUBNODES_START)
(OBJECT_HARD_REGS_SUBNODES_NUM): New macros.
(struct target_ira_int): New members x_ira_max_memory_move_cost,
x_ira_max_register_move_cost, x_ira_max_may_move_in_cost,
x_ira_max_may_move_out_cost, x_ira_reg_allocno_class_p,
x_ira_reg_pressure_class_p, x_ira_important_class_nums,
x_ira_reg_class_superunion. Rename x_prohibited_class_mode_reg to
x_ira_prohibited_class_mode_reg. Rename x_ira_reg_class_union to
x_ira_reg_class_subunion.
(ira_max_memory_move_cost, ira_max_register_move_cost)
(ira_max_may_move_in_cost, ira_max_may_move_out_cost)
(ira_reg_allocno_class_p, ira_reg_pressure_class_p)
(ira_important_class_nums, ira_reg_class_superunion): New macros.
(prohibited_class_mode_regs): Rename to
ira_prohibited_class_mode_regs.
(ira_reg_class_union): Rename to ira_reg_class_subunion.
(ira_debug_class_cover): Rename to ira_debug_allocno_classes.
(ira_set_allocno_cover_class): Rename to ira_set_allocno_class.
(ira_tune_allocno_costs_and_cover_classes): Rename to
ira_tune_allocno_costs.
(ira_debug_hard_regs_forest): New.
(ira_object_conflict_iter_init, ira_object_conflict_iter_cond)
(ira_object_conflict_iter_next): Fix comments.
(ira_hard_reg_set_intersection_p, hard_reg_set_size): New
functions.
(ira_allocate_and_set_costs, ira_allocate_and_copy_costs): Rename
cover_class to aclass.
(ira_allocate_and_accumulate_costs): Ditto.
(ira_allocate_and_set_or_copy_costs): Ditto.
* opts.c (decode_options): Remove ira_cover_class check.
* ira-color.c: Remove mentioning cover classes from the file. Use
ALLOCNO_CLASS, ALLOCNO_CLASS_COST, and ALLOCNO_UPDATED_CLASS_COST
instead of ALLOCNO_COVER_CLASS, ALLOCNO_COVER_CLASS_COST, and
ALLOCNO_UPDATED_COVER_CLASS_COST. Fix formatting.
(splay-tree.h): Remove include.
(allocno_coalesced_p, processed_coalesced_allocno_bitmap): Move
before copy_freq_compare_func.
(allocnos_for_spilling, removed_splay_allocno_vec): Remove.
(object_hard_regs_vec, object_hard_regs_htab, node_check_tick):
New definitions.
(hard_regs_roots, hard_regs_node_vec): Ditto.
(object_hard_regs_hash, object_hard_regs_eq, find_hard_regs): Ditto.
(insert_hard_regs, init_object_hard_regs, add_object_hard_regs): Ditto.
(finish_object_hard_regs, object_hard_regs_compare): Ditto.
(create_new_object_hard_regs_node): Ditto.
(add_new_object_hard_regs_node_to_forest): Ditto.
(add_object_hard_regs_to_forest, collect_object_hard_regs_cover):
Ditto.
(setup_object_hard_regs_nodes_parent, first_common_ancestor_node):
Ditto.
(print_hard_reg_set, print_hard_regs_subforest): Ditto.
(print_hard_regs_forest, ira_debug_hard_regs_forest): Ditto.
(remove_unused_object_hard_regs_nodes): Ditto.
(enumerate_object_hard_regs_nodes): Ditto.
(object_hard_regs_nodes_num, object_hard_regs_nodes): Ditto.
(object_hard_regs_subnode_t): Ditto.
(struct object_hard_regs_subnode): Ditto.
(object_hard_regs_subnodes, object_hard_regs_subnode_index): Ditto.
(setup_object_hard_regs_subnode_index): Ditto.
(get_object_hard_regs_subnodes_num): Ditto.
(form_object_hard_regs_nodes_forest): Ditto.
(finish_object_hard_regs_nodes_tree): Ditto.
(finish_object_hard_regs_nodes_forest): Ditto.
(allocnos_have_intersected_live_ranges_p): Rename to
allocnos_conflict_by_live_ranges_p. Move before
copy_freq_compare_func.
(pseudos_have_intersected_live_ranges_p): Rename to
conflict_by_live_ranges_p. Move before copy_freq_compare_func.
(setup_left_conflict_sizes_p, update_left_conflict_sizes_p): Ditto.
(empty_profitable_hard_regs, setup_profitable_hard_regs): Ditto.
(update_copy_costs): Remove assert. Skip cost update if the hard
reg does not belong the class.
(assign_hard_reg): Process only profitable hard regs.
(uncolorable_allocnos_num): Make it scalar.
(allocno_spill_priority): Use ALLOCNO_EXCESS_PRESSURE_POINTS_NUM
and ira_reg_class_max_nregs instead of ALLOCNO_LEFT_CONFLICTS_SIZE
and ira_reg_class_max_nregs.
(bucket_allocno_compare_func): Check frequency first.
(sort_bucket): Add compare function as a parameter.
(add_allocno_to_ordered_bucket): Assume no coalesced allocnos.
(uncolorable_allocnos_splay_tree, USE_SPLAY_P): Remove.
(push_allocno_to_stack): Rewrite for checking new allocno
colorability.
(remove_allocno_from_bucket_and_push): Print cost too. Remove
assert.
(push_only_colorable): Pass new parameter to sort_bucket.
(push_allocno_to_spill): Remove.
(allocno_spill_priority_compare): Make it inline and rewrite.
(splay_tree_allocate, splay_tree_free): Remove.
(allocno_spill_sort_compare): New function.
(push_allocnos_to_stack): Sort allocnos for spilling once. Don't
build and use splay tree. Choose first allocno in uncolorable
allocno bucket to spill. Remove setting spill cost.
(all_conflicting_hard_regs): Remove.
(setup_allocno_available_regs_num): Check only profitable hard
regs. Print info about hard regs nodes.
(setup_allocno_left_conflicts_size): Remove.
(put_allocno_into_bucket): Don't call
setup_allocno_left_conflicts_size. Use
setup_left_conflict_sizes_p.
(improve_allocation): New.
(color_allocnos): Call setup_profitable_hard_regs,
form_object_hard_regs_nodes_forest, improve_allocation,
finish_object_hard_regs_nodes_forest. Setup spill cost.
(print_loop_title): Use pressure classes.
(color_allocnso): Ditto.
(do_coloring): Remove allocation and freeing splay_tree_node_pool
and allocnos_for_spilling.
(ira_sort_regnos_for_alter_reg): Don't setup members
{first,next}_coalesced_allocno.
(color): Remove allocating and freeing removed_splay_allocno_vec.
(fast_allocation): Use ira_prohibited_class_mode_regs instead of
prohibited_class_mode_regs.
* ira-lives.c: Remove mentioning cover classes from the file. Fix
formatting.
(update_allocno_pressure_excess_length): Use pressure classes.
(inc_register_pressure, dec_register_pressure): Check for pressure
class.
(mark_pseudo_regno_live, mark_pseudo_regno_subword_live): Use
pressure class. Use ira_reg_class_nregs instead of
ira_reg_class_max_nregs.
(mark_pseudo_regno_dead, mark_pseudo_regno_subword_dead): Ditto.
(mark_hard_reg_live, mark_hard_reg_dead): Use pressure class.
(single_reg_class): Use ira_reg_class_nregs instead of
ira_reg_class_max_nregs.
(process_bb_node_lives): Use pressure classes.
* ira-emit.c: Remove mentioning cover classes from the file. Use
ALLOCNO_CLASS instead of ALLOCNO_COVER_CLASS. Fix formatting.
(change_loop): Use pressure classes.
(modify_move_list): Call ira_set_allocno_class instead of
ira_set_allocno_cover_class.
* ira-build.c: Remove mentioning cover classes from the file. Use
ALLOCNO_CLASS and ALLOCNO_CLASS_COST instead of
ALLOCNO_COVER_CLASS and ALLOCNO_COVER_CLASS_COST. Use
ALLOCNO_UPDATED_CLASS_COST instead of
ALLOCNO_UPDATED_COVER_CLASS_COST. Fix formatting.
(ira_create_object): Initiate OBJECT_PROFITABLE_HARD_REGS.
(ira_create_allocno): Remove initialization of
ALLOCNO_SPLAY_REMOVED_P, ALLOCNO_LEFT_CONFLICT_SIZE. Initialize
ALLOCNO_COLORABLE_P.
(ira_set_allocno_cover_class): Rename to ira_set_allocno_class.
Update conflict regs for the objects.
(create_cap_allocno): Remove assert. Don't propagate
ALLOCNO_AVAILABLE_REGS_NUM.
(ira_free_allocno_costs): New function.
(finish_allocno): Change a part of code into call of
ira_free_allocno_costs.
(low_pressure_loop_node_p): Use pressure classes.
(object_range_compare_func): Don't compare classes.
(setup_min_max_conflict_allocno_ids): Ditto.
* loop-invariant.c: Remove mentioning cover classes from the file.
Use ira_pressure_classes and ira_pressure_classes_num instead of
ira_reg_class_cover_size and ira_reg_class_cover. Fix formatting.
(get_cover_class_and_nregs): Rename to
get_cover_pressure_and_nregs. Use ira_reg_class_max_nregs instead
of ira_reg_class_nregs. Use reg_allocno_class instead of
reg_cover_class.
(get_inv_cost): Use instead ira_stack_reg_pressure_class of
STACK_REG_COVER_CLASS.
(get_regno_cover_class): Rename to get_regno_pressure_class.
(move_loop_invariants): Initialize and finalize regstat.
* ira.c: Remove mentioning cover classes from the file. Add
comments about coloring without cover classes. Use ALLOCNO_CLASS
instead of ALLOCNO_COVER_CLASS. Fix formatting.
(alloc_reg_class_subclasses, setup_reg_subclasses): Move it before
setup_class_subset_and_memory_move_costs.
(setup_stack_reg_pressure_class, setup_pressure_classes): New.
(setup_cover_and_important_classes): Rename to
setup_allocno_and_important_classes.
(setup_class_translate_array): New.
(setup_class_translate): Call it for allocno and pressure classes.
(cover_class_order): Rename to allocno_class_order.
(comp_reg_classes_func): Use ira_allocno_class_translate instead
of ira_class_translate.
(reorder_important_classes): Set up ira_important_class_nums.
(setup_reg_class_relations): Set up ira_reg_class_superunion.
(print_class_cover): Rename to print_classes. Add parameter.
(ira_debug_class_cover): Rename to ira_debug_allocno_classes.
Print pressure classes too.
(find_reg_class_closure): Rename to find_reg_classes. Don't call
setup_reg_subclasses.
(ira_hard_regno_cover_class): Rename to
ira_hard_regno_allocno_class.
(ira_reg_class_nregs): Rename to ira_reg_class_max_nregs.
(setup_prohibited_class_mode_regs): Use
ira_prohibited_class_mode_regs instead of
prohibited_class_mode_regs.
(clarify_prohibited_class_mode_regs): New function.
(ira_init_register_move_cost): Set up ira_max_register_move_cost,
ira_max_may_move_in_cost, and ira_max_may_move_out_cost.
(ira_init_once): Initialize them.
(free_register_move_costs): Process them.
(ira_init): Move calls of find_reg_classes and
setup_hard_regno_aclass after setup_prohibited_class_mode_regs.
Call clarify_prohibited_class_mode_regs.
(ira_no_alloc_reg): Remove.
(too_high_register_pressure_p): Use pressure classes.
* sched-deps.c: Remove mentioning cover classes from the file.
Use ira_reg_pressure_cover instead of ira_reg_class_cover. Use
ira_pressure_classes and ira_pressure_classes_num instead of
ira_reg_class_cover_size and ira_reg_class_cover.
(mark_insn_hard_regno_birth, mark_hard_regno_death): Use
sched_regno_pressure_class instead of sched_regno_cover_class.
(mark_insn_pseudo_birth, mark_pseudo_death): Ditto. Use
ira_reg_class_max_nregs instead of ira_reg_class_nregs.
* ira.h: Add 2010 to Copyright.
(ira_no_alloc_reg): Remove external.
(struct target_ira): Rename x_ira_hard_regno_cover_class,
x_ira_reg_class_cover_size, x_ira_reg_class_cover, and
x_ira_class_translate to x_ira_hard_regno_allocno_class,
x_ira_allocno_classes_num, x_ira_allocno_classes, and
x_ira_allocno_class_translate. Add x_ira_pressure_classes_num,
x_ira_pressure_classes, x_ira_pressure_class_translate, and
x_ira_stack_reg_pressure_class. Rename x_ira_reg_class_nregs to
x_ira_reg_class_max_nregs. Add x_ira_reg_class_min_nregs and
x_ira_no_alloc_regs.
(ira_hard_regno_cover_class): Rename to
ira_hard_regno_allocno_class.
(ira_reg_class_cover_size, ira_reg_class_cover): Rename to
ira_allocno_classes_num and ira_allocno_classes.
(ira_class_translate): Rename to ira_allocno_class_translate.
(ira_pressure_classes_num, ira_pressure_classes): New definitions.
(ira_pressure_class_translate, ira_stack_reg_pressure_class): Ditto.
(ira_reg_class_nregs): Rename to ira_reg_class_max_nregs.
(ira_reg_class_min_nregs, ira_stack_reg_pressure_class): New
(ira_no_alloc_regs): New.
* ira-costs.c: Add 2010 to Copyright. Remove mentioning cover
classes from the file. Use ALLOCNO_CLASS instead of
ALLOCNO_COVER_CLASS. Use ALLOCNO_CLASS_COST instead of
ALLOCNO_COVER_CLASS_COST.
(regno_cover_class): Rename to regno_aclass.
(record_reg_classes): Use ira_reg_class_subunion instead of
ira_reg_class_union.
(record_address_regs): Check overflow.
(scan_one_insn): Ditto.
(print_allocno_costs): Print total mem cost fore regional
allocation.
(print_pseudo_costs): Use REG_N_REFS.
(find_costs_and_classes): Use classes intersected with them on the
1st pass. Check overflow. Use ira_reg_class_subunion instead of
ira_reg_class_union. Use ira_allocno_class_translate and
regno_aclass instead of ira_class_translate and regno_cover_class.
Modify code for finding regno_aclass. Setup preferred classes for
the next pass.
(setup_allocno_cover_class_and_costs): Rename to
setup_allocno_class_and_costs. Use regno_aclass instead of
regno_cover_class. Use ira_set_allocno_class instead of
ira_set_allocno_cover_class.
(init_costs, finish_costs): Use regno_aclass instead of
regno_cover_class.
(ira_costs): Use setup_allocno_class_and_costs instead of
setup_allocno_cover_class_and_costs.
(ira_tune_allocno_costs_and_cover_classes): Rename to
ira_tune_allocno_costs. Check overflow. Skip conflict hard regs
by processing objects. Use ira_reg_class_max_nregs instead of
ira_reg_class_nregs.
* rtl.h (reg_cover_class): Rename to reg_allocno_class.
* sched-int.h: Remove mentioning cover classes from the file.
(sched_regno_cover_class): Rename to sched_regno_pressure_class.
* reginfo.c: Add 2010 to Copyright. Remove mentioning cover
classes from the file.
(struct reg_pref): Rename coverclass into allocnoclass.
(reg_cover_class): Rename to reg_allocno_class.
* Makefile.in (ira-color.o): Remove SPLAY_TREE_H from
dependencies.
* config/alpha/alpha.h (IRA_COVER_CLASSES): Remove.
* config/arm/arm.h (IRA_COVER_CLASSES): Ditto.
* config/avr/avr.h (IRA_COVER_CLASSES): Ditto.
* config/bfin/bfin.h (IRA_COVER_CLASSES): Ditto.
* config/cris/cris.h (IRA_COVER_CLASSES): Ditto.
* config/fr30/fr30.h (IRA_COVER_CLASSES): Ditto.
* config/frv/frv.h (IRA_COVER_CLASSES): Ditto.
* config/h8300/h8300.h (IRA_COVER_CLASSES): Ditto.
* config/i386/i386.h (STACK_REG_COVER_CLASS): Ditto.
* config/i386/i386.c (TARGET_IRA_COVER_CLASSES)
(i386_ira_cover_classes): Ditto.
* config/ia64/ia64.h (IRA_COVER_CLASSES): Ditto.
* config/iq2000/iq2000.h (IRA_COVER_CLASSES): Ditto.
* config/m32r/m32r.h (IRA_COVER_CLASSES): Ditto.
* config/m68k/m68k.h (IRA_COVER_CLASSES): Ditto.
* config/mcore/mcore.h (IRA_COVER_CLASSES): Ditto.
* config/mep/mep.h (IRA_COVER_CLASSES): Ditto.
* config/mips/mips.c (TARGET_IRA_COVER_CLASSES)
(mips_ira_cover_classes): Ditto.
* config/mn10300/mn10300.h (IRA_COVER_CLASSES): Ditto.
* config/moxie/moxie.h (IRA_COVER_CLASSES): Ditto.
* config/pa/pa64-regs.h (IRA_COVER_CLASSES): Ditto.
* config/pa/pa32-regs.h (IRA_COVER_CLASSES): Ditto.
* config/picochip/picochip.h (IRA_COVER_CLASSES): Ditto.
* config/rs6000/rs6000.h (IRA_COVER_CLASSES_PRE_VSX)
(IRA_COVER_CLASSES_VSX): Ditto.
* config/rs6000/rs6000.c (TARGET_IRA_COVER_CLASSES)
(rs6000_ira_cover_classes): Ditto.
* config/rx/rx.h (IRA_COVER_CLASSES): Ditto.
* config/s390/s390.h (IRA_COVER_CLASSES): Ditto.
* config/score/score.h (IRA_COVER_CLASSES): Ditto.
* config/sh/sh.h (IRA_COVER_CLASSES): Ditto.
* config/sparc/sparc.h (IRA_COVER_CLASSES): Ditto.
* config/spu/spu.h (IRA_COVER_CLASSES): Ditto.
* config/stormy16/stormy16.h (IRA_COVER_CLASSES): Ditto.
* config/v850/v850.h (IRA_COVER_CLASSES): Ditto.
* config/vax/vax.h (IRA_COVER_CLASSES): Ditto.
* config/xtensa/xtensa.h (IRA_COVER_CLASSES): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@171649 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
34 files changed, 0 insertions, 368 deletions
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h index 14fc731ef24..bfb443c7088 100644 --- a/gcc/config/alpha/alpha.h +++ b/gcc/config/alpha/alpha.h @@ -511,19 +511,6 @@ enum reg_class { {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \ {0xffffffff, 0xffffffff} } -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, FLOAT_REGS, LIM_REG_CLASSES \ -} - /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index add8eced3ed..276005c3da0 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1152,20 +1152,6 @@ enum reg_class or could index an array. */ #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\ - LIM_REG_CLASSES \ -} - /* FPA registers can't do subreg as all values are reformatted to internal precision. In VFPv1, VFP registers could only be accessed in the mode they were set, so subregs would be invalid there too. However, we don't diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index 37fb3ed818a..47bb3fba43c 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -296,19 +296,6 @@ enum reg_class { #define REGNO_REG_CLASS(R) avr_regno_reg_class(R) -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, LIM_REG_CLASSES \ -} - #define BASE_REG_CLASS (reload_completed ? BASE_POINTER_REGS : POINTER_REGS) #define INDEX_REG_CLASS NO_REGS diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h index 441e202fc5b..6ebaa44f566 100644 --- a/gcc/config/bfin/bfin.h +++ b/gcc/config/bfin/bfin.h @@ -664,19 +664,6 @@ enum reg_class : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ : NO_REGS) -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - MOST_REGS, AREGS, CCREGS, LIM_REG_CLASSES \ -} - /* When this hook returns true for MODE, the compiler allows registers explicitly used in the rtl to be used as spill registers but prevents the compiler from extending the lifetime of these diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index e8172bb1195..c8b7d2ff4c5 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -550,8 +550,6 @@ enum reg_class #define INDEX_REG_CLASS GENERAL_REGS -#define IRA_COVER_CLASSES { GENERAL_REGS, SPECIAL_REGS, LIM_REG_CLASSES } - #define REG_CLASS_FROM_LETTER(C) \ ( \ (C) == 'a' ? ACR_REGS : \ diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h index d20d7fb79c3..9f8be86846d 100644 --- a/gcc/config/fr30/fr30.h +++ b/gcc/config/fr30/fr30.h @@ -290,11 +290,6 @@ enum reg_class #define GENERAL_REGS REAL_REGS #define N_REG_CLASSES ((int) LIM_REG_CLASSES) -#define IRA_COVER_CLASSES \ -{ \ - REAL_REGS, MULTIPLY_64_REG, LIM_REG_CLASSES \ -} - /* An initializer containing the names of the register classes as C string constants. These names are used in writing some of the debugging dumps. */ #define REG_CLASS_NAMES \ diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h index 299a85676ba..2c1abf3de90 100644 --- a/gcc/config/frv/frv.h +++ b/gcc/config/frv/frv.h @@ -970,21 +970,6 @@ enum reg_class { 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0x1fff}, /* ALL_REGS */\ } -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GPR_REGS, FPR_REGS, ACC_REGS, ICR_REGS, FCR_REGS, ICC_REGS, FCC_REGS, \ - ACCG_REGS, SPR_REGS, \ - LIM_REG_CLASSES \ -} - /* A C expression whose value is a register class containing hard register REGNO. In general there is more than one such class; choose a class which is "minimal", meaning that no smaller class also contains the register. */ diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h index 57fffda2297..70777c060b1 100644 --- a/gcc/config/h8300/h8300.h +++ b/gcc/config/h8300/h8300.h @@ -330,19 +330,6 @@ enum reg_class { { "NO_REGS", "COUNTER_REGS", "SOURCE_REGS", "DESTINATION_REGS", \ "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" } -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, MAC_REGS, LIM_REG_CLASSES \ -} - /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 854223898d8..a985b2b7691 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -28434,22 +28434,6 @@ ix86_free_from_memory (enum machine_mode mode) } } -/* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer - SSE_REGS to FLOAT_REGS if their costs for a pseudo are the - same. */ -static const reg_class_t * -i386_ira_cover_classes (void) -{ - static const reg_class_t sse_fpmath_classes[] = { - GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES - }; - static const reg_class_t no_sse_fpmath_classes[] = { - GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES - }; - - return TARGET_SSE_MATH ? sse_fpmath_classes : no_sse_fpmath_classes; -} - /* Implement TARGET_PREFERRED_RELOAD_CLASS. Put float CONST_DOUBLE in the constant pool instead of fp regs. @@ -35349,9 +35333,6 @@ ix86_autovectorize_vector_sizes (void) #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p -#undef TARGET_IRA_COVER_CLASSES -#define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes - #undef TARGET_FRAME_POINTER_REQUIRED #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 12edeba97f7..326b8bc499d 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -870,9 +870,6 @@ enum target_cpu_default || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \ || (MODE) == XFmode) -/* Cover class containing the stack registers. */ -#define STACK_REG_COVER_CLASS FLOAT_REGS - /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index ed618f29fc2..a894df8dff7 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -774,19 +774,6 @@ enum reg_class 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \ } -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - PR_REGS, BR_REGS, AR_M_REGS, AR_I_REGS, GR_REGS, FR_REGS, LIM_REG_CLASSES \ -} - /* A C expression whose value is a register class containing hard register REGNO. In general there is more than one such class; choose a class which is "minimal", meaning that no smaller class also contains the register. */ diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h index 62cddea444e..8a3c653c455 100644 --- a/gcc/config/iq2000/iq2000.h +++ b/gcc/config/iq2000/iq2000.h @@ -209,11 +209,6 @@ enum reg_class #define N_REG_CLASSES (int) LIM_REG_CLASSES -#define IRA_COVER_CLASSES \ -{ \ - GR_REGS, LIM_REG_CLASSES \ -} - #define REG_CLASS_NAMES \ { \ "NO_REGS", \ diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index a43e2956c94..31c6cb1e2fb 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -459,11 +459,6 @@ enum reg_class NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; -#define IRA_COVER_CLASSES \ -{ \ - ACCUM_REGS, GENERAL_REGS, LIM_REG_CLASSES \ -} - #define N_REG_CLASSES ((int) LIM_REG_CLASSES) /* Give names of register classes as strings for dump file. */ diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index 71b7c4f273f..e53737933b4 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -496,10 +496,6 @@ extern enum reg_class regno_reg_class[]; #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2) -#define IRA_COVER_CLASSES \ -{ \ - ALL_REGS, LIM_REG_CLASSES \ -} /* Stack layout; function entry, exit and calling. */ diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index 54c12ef3dd8..fa3909e628f 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -324,11 +324,6 @@ enum reg_class #define N_REG_CLASSES (int) LIM_REG_CLASSES -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, C_REGS, LIM_REG_CLASSES \ -} - /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ diff --git a/gcc/config/mep/mep.h b/gcc/config/mep/mep.h index 5244bb38a4b..ed2d6602d3d 100644 --- a/gcc/config/mep/mep.h +++ b/gcc/config/mep/mep.h @@ -407,8 +407,6 @@ enum reg_class #define REGNO_REG_CLASS(REGNO) (enum reg_class) mep_regno_reg_class (REGNO) -#define IRA_COVER_CLASSES { GENERAL_REGS, CONTROL_REGS, CR_REGS, CCR_REGS, LIM_REG_CLASSES } - #define BASE_REG_CLASS GENERAL_REGS #define INDEX_REG_CLASS GENERAL_REGS diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 0692902e845..643e507fddf 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -11017,29 +11017,6 @@ mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in) + memory_move_secondary_cost (mode, rclass, in)); } -/* Implement TARGET_IRA_COVER_CLASSES. */ - -static const reg_class_t * -mips_ira_cover_classes (void) -{ - static const reg_class_t acc_classes[] = { - GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS, - ST_REGS, LIM_REG_CLASSES - }; - static const reg_class_t no_acc_classes[] = { - GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS, - ST_REGS, LIM_REG_CLASSES - }; - - /* Don't allow the register allocators to use LO and HI in MIPS16 mode, - which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS - as a cover class only works well when we keep per-register costs. - Using it when not optimizing can cause us to think accumulators - have the same cost as GPRs in cases where GPRs are actually much - cheaper. */ - return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes; -} - /* Return the register class required for a secondary register when copying between one of the registers in RCLASS and value X, which has mode MODE. X is the source of the move if IN_P, otherwise it @@ -16618,9 +16595,6 @@ mips_shift_truncation_mask (enum machine_mode mode) #undef TARGET_DWARF_REGISTER_SPAN #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span -#undef TARGET_IRA_COVER_CLASSES -#define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes - #undef TARGET_ASM_FINAL_POSTSCAN_INSN #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h index ac23f585861..f660dca5aa9 100644 --- a/gcc/config/mn10300/mn10300.h +++ b/gcc/config/mn10300/mn10300.h @@ -309,19 +309,6 @@ enum reg_class { 0xffffffff, 0xfffff } /* ALL_REGS */ \ } -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, FP_REGS, MDR_REGS, LIM_REG_CLASSES \ -} - /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression diff --git a/gcc/config/moxie/moxie.h b/gcc/config/moxie/moxie.h index 41f66cb6baa..1b5e0a3f8aa 100644 --- a/gcc/config/moxie/moxie.h +++ b/gcc/config/moxie/moxie.h @@ -135,15 +135,6 @@ enum reg_class }; -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ -#define IRA_COVER_CLASSES { GENERAL_REGS, LIM_REG_CLASSES } - #define REG_CLASS_CONTENTS \ { { 0x00000000 }, /* Empty */ \ { 0x0003FFFF }, /* $fp, $sp, $r0 to $r13, ?fp */ \ diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h index 7e8e05df981..d207c0a7275 100644 --- a/gcc/config/pa/pa32-regs.h +++ b/gcc/config/pa/pa32-regs.h @@ -294,19 +294,6 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \ {0xfffffffe, 0xffffffff, 0x03ffffff}} /* ALL_REGS */ -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \ -} - /* Defines invalid mode changes. */ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h index 23dc7780e4e..810e945f6b4 100644 --- a/gcc/config/pa/pa64-regs.h +++ b/gcc/config/pa/pa64-regs.h @@ -230,19 +230,6 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, {0x00000000, 0x10000000}, /* SHIFT_REGS */ \ {0xfffffffe, 0x3fffffff}} /* ALL_REGS */ -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \ -} - /* Defines invalid mode changes. */ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ diff --git a/gcc/config/picochip/picochip.h b/gcc/config/picochip/picochip.h index 5f6bc7b2c07..cb0a8f93335 100644 --- a/gcc/config/picochip/picochip.h +++ b/gcc/config/picochip/picochip.h @@ -292,19 +292,6 @@ enum reg_class #define N_REG_CLASSES (int) LIM_REG_CLASSES -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GR_REGS, LIM_REG_CLASSES \ -} - /* The names of the register classes */ #define REG_CLASS_NAMES \ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index b1efc0dc9d3..8b1d4122d87 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1208,8 +1208,6 @@ static reg_class_t rs6000_secondary_reload (bool, rtx, reg_class_t, enum machine_mode, struct secondary_reload_info *); -static const reg_class_t *rs6000_ira_cover_classes (void); - const int INSN_NOT_AVAILABLE = -1; static enum machine_mode rs6000_eh_return_filter_mode (void); static bool rs6000_can_eliminate (const int, const int); @@ -1636,9 +1634,6 @@ static const struct default_options rs6000_option_optimization_table[] = #undef TARGET_SECONDARY_RELOAD #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload -#undef TARGET_IRA_COVER_CLASSES -#define TARGET_IRA_COVER_CLASSES rs6000_ira_cover_classes - #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p @@ -15288,26 +15283,6 @@ rs6000_secondary_reload_ppc64 (rtx reg, rtx mem, rtx scratch, bool store_p) return; } -/* Target hook to return the cover classes for Integrated Register Allocator. - Cover classes is a set of non-intersected register classes covering all hard - registers used for register allocation purpose. Any move between two - registers of a cover class should be cheaper than load or store of the - registers. The value is array of register classes with LIM_REG_CLASSES used - as the end marker. - - We need two IRA_COVER_CLASSES, one for pre-VSX, and the other for VSX to - account for the Altivec and Floating registers being subsets of the VSX - register set under VSX, but distinct register sets on pre-VSX machines. */ - -static const reg_class_t * -rs6000_ira_cover_classes (void) -{ - static const reg_class_t cover_pre_vsx[] = IRA_COVER_CLASSES_PRE_VSX; - static const reg_class_t cover_vsx[] = IRA_COVER_CLASSES_VSX; - - return (TARGET_VSX) ? cover_vsx : cover_pre_vsx; -} - /* Allocate a 64-bit stack slot to be used for copying SDmode values through if this function has any SDmode references. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 49134568b71..0193db52eb2 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1252,34 +1252,6 @@ enum reg_class { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \ } -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. - - We need two IRA_COVER_CLASSES, one for pre-VSX, and the other for VSX to - account for the Altivec and Floating registers being subsets of the VSX - register set. */ - -#define IRA_COVER_CLASSES_PRE_VSX \ -{ \ - GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */ \ - /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \ - /* MQ_REGS, LINK_REGS, CTR_REGS, */ \ - CR_REGS, CA_REGS, LIM_REG_CLASSES \ -} - -#define IRA_COVER_CLASSES_VSX \ -{ \ - GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS, \ - /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \ - /* MQ_REGS, LINK_REGS, CTR_REGS, */ \ - CR_REGS, CA_REGS, LIM_REG_CLASSES \ -} - /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h index bd54a2b954f..f9ea2093007 100644 --- a/gcc/config/rx/rx.h +++ b/gcc/config/rx/rx.h @@ -187,11 +187,6 @@ enum reg_class { 0x0000ffff } /* All registers. */ \ } -#define IRA_COVER_CLASSES \ - { \ - GR_REGS, LIM_REG_CLASSES \ - } - #define SMALL_REGISTER_CLASSES 0 #define N_REG_CLASSES (int) LIM_REG_CLASSES #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \ diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h index c6ba4ff2453..8825ae224f4 100644 --- a/gcc/config/s390/s390.h +++ b/gcc/config/s390/s390.h @@ -468,19 +468,6 @@ enum reg_class { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \ } -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, FP_REGS, CC_REGS, ACCESS_REGS, LIM_REG_CLASSES \ -} - /* In some case register allocation order is not enough for IRA to generate a good code. The following macro (if defined) increases cost of REGNO for a pseudo approximately by pseudo usage frequency diff --git a/gcc/config/score/score.h b/gcc/config/score/score.h index 4554e267344..c66e0e934ce 100644 --- a/gcc/config/score/score.h +++ b/gcc/config/score/score.h @@ -390,18 +390,6 @@ enum reg_class also contains the register. */ #define REGNO_REG_CLASS(REGNO) (enum reg_class) score_reg_class (REGNO) -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ -#define IRA_COVER_CLASSES \ -{ \ - G32_REGS, CE_REGS, SP_REGS, LIM_REG_CLASSES \ -} - /* A macro whose definition is the name of the class to which a valid base register must belong. A base register is one used in an address which is the register value plus a displacement. */ diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 4579af32736..d45f8c08001 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -1133,20 +1133,6 @@ enum reg_class extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \ - FPUL_REGS, LIM_REG_CLASSES \ -} - /* When this hook returns true for MODE, the compiler allows registers explicitly used in the rtl to be used as spill registers but prevents the compiler from extending the lifetime of these diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 9b68f13f19a..96733bfe24b 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -972,19 +972,6 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ - -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, EXTRA_FP_REGS, FPCC_REGS, LIM_REG_CLASSES \ -} - /* Defines invalid mode changes. Borrowed from pa64-regs.h. SImode loads to floating-point registers are not zero-extended. diff --git a/gcc/config/spu/spu.h b/gcc/config/spu/spu.h index 51bfa5131aa..b3bdcf5abdf 100644 --- a/gcc/config/spu/spu.h +++ b/gcc/config/spu/spu.h @@ -196,9 +196,6 @@ enum reg_class { LIM_REG_CLASSES }; -/* SPU is simple, it really only has one class of registers. */ -#define IRA_COVER_CLASSES { GENERAL_REGS, LIM_REG_CLASSES } - #define N_REG_CLASSES (int) LIM_REG_CLASSES #define REG_CLASS_NAMES \ diff --git a/gcc/config/stormy16/stormy16.h b/gcc/config/stormy16/stormy16.h index a838b8acf83..53f4d2d7b65 100644 --- a/gcc/config/stormy16/stormy16.h +++ b/gcc/config/stormy16/stormy16.h @@ -179,11 +179,6 @@ enum reg_class #define N_REG_CLASSES ((int) LIM_REG_CLASSES) -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, LIM_REG_CLASSES \ -} - #define REG_CLASS_NAMES \ { \ "NO_REGS", \ diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h index d1c4320e39e..1171399c4cf 100644 --- a/gcc/config/v850/v850.h +++ b/gcc/config/v850/v850.h @@ -304,11 +304,6 @@ enum reg_class #define N_REG_CLASSES (int) LIM_REG_CLASSES -#define IRA_COVER_CLASSES \ -{ \ - GENERAL_REGS, LIM_REG_CLASSES \ -} - /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ diff --git a/gcc/config/vax/vax.h b/gcc/config/vax/vax.h index 272dfbbc342..15b7daa7b7e 100644 --- a/gcc/config/vax/vax.h +++ b/gcc/config/vax/vax.h @@ -226,15 +226,6 @@ enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES }; #define REG_CLASS_NAMES \ { "NO_REGS", "ALL_REGS" } -/* The following macro defines cover classes for Integrated Register - Allocator. Cover classes is a set of non-intersected register - classes covering all hard registers used for register allocation - purpose. Any move between two registers of a cover class should be - cheaper than load or store of the registers. The macro value is - array of register classes with LIM_REG_CLASSES used as the end - marker. */ -#define IRA_COVER_CLASSES { ALL_REGS, LIM_REG_CLASSES } - /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index 0a096cdb5e4..c9ff80c4664 100644 --- a/gcc/config/xtensa/xtensa.h +++ b/gcc/config/xtensa/xtensa.h @@ -432,11 +432,6 @@ enum reg_class { 0xffffffff, 0x0000000f } /* all registers */ \ } -#define IRA_COVER_CLASSES \ -{ \ - BR_REGS, FP_REGS, ACC_REG, AR_REGS, LIM_REG_CLASSES \ -} - /* A C expression whose value is a register class containing hard register REGNO. In general there is more that one such class; choose a class which is "minimal", meaning that no smaller class |