diff options
| author | msebor <msebor@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-10-21 22:24:41 +0000 |
|---|---|---|
| committer | msebor <msebor@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-10-21 22:24:41 +0000 |
| commit | 8fb42bbc39752a5b25215ddfe32682bfe2bf3902 (patch) | |
| tree | 0e86ee5c584e34b06f641c070503e72ef5231aaf /gcc/config | |
| parent | cfec10ded5e70b421fc269e6255c5f77c1d6743b (diff) | |
| download | gcc-8fb42bbc39752a5b25215ddfe32682bfe2bf3902.tar.gz | |
Improve --help output to generate references to option aliases.
gcc/
PR driver/68043
* opts.c (undocumented_msg, use_diagnosed_msg): New globals.
(print_filtered_help): Reference aliased option's name and encourage
readers to use it in preference to the alias if the former is not
documented. Mention when using an option is diagnosed.
* gcc.c (display_help): End each sentence with a period.
* ada/gcc-interface/lang.opt: End each sentence that describes
an option with a period.
* c-family/c.opt: Same.
* common.opt: Same.
* config/aarch64/aarch64.opt: Same.
* config/alpha/alpha.opt: Same.
* config/arc/arc.opt: Same.
* config/arm/arm.opt: Same.
* config/avr/avr.opt: Same.
* config/bfin/bfin.opt: Same.
* config/c6x/c6x.opt: Same.
* config/cr16/cr16.opt: Same.
* config/cris/cris.opt: Same.
* config/cris/linux.opt: Same.
* config/darwin.opt: Same.
* config/epiphany/epiphany.opt: Same.
* config/fr30/fr30.opt: Same.
* config/frv/frv.opt: Same.
* config/ft32/ft32.opt: Same.
* config/g.opt: Same.
* config/h8300/h8300.opt: Same.
* config/i386/cygming.opt: Same.
* config/i386/djgpp.opt: Same.
* config/i386/i386.opt: Same.
* config/i386/interix.opt: Same.
* config/i386/mingw-w64.opt: Same.
* config/i386/mingw.opt: Same.
* config/ia64/ia64.opt: Same.
* config/ia64/ilp32.opt: Same.
* config/iq2000/iq2000.opt: Same.
* config/linux.opt: Same.
* config/lm32/lm32.opt: Same.
* config/lynx.opt: Same.
* config/m32c/m32c.opt: Same.
* config/m32r/m32r.opt: Same.
* config/m68k/ieee.opt: Same.
* config/m68k/m68k.opt: Same.
* config/mcore/mcore.opt: Same.
* config/mep/mep.opt: Same.
* config/microblaze/microblaze.opt: Same.
* config/mips/mips.opt: Same.
* config/mmix/mmix.opt: Same.
* config/mn10300/mn10300.opt: Same.
* config/moxie/moxie.opt: Same.
* config/msp430/msp430.opt: Same.
* config/nios2/elf.opt: Same.
* config/nios2/nios2.opt: Same.
* config/nvptx/nvptx.opt: Same.
* config/pa/pa-hpux.opt: Same.
* config/pa/pa-hpux1010.opt: Same.
* config/pa/pa-hpux1111.opt: Same.
* config/pa/pa-hpux1131.opt: Same.
* config/pa/pa.opt: Same.
* config/pa/pa64-hpux.opt: Same.
* config/pdp11/pdp11.opt: Same.
* config/rl78/rl78.opt: Same.
* config/rs6000/476.opt: Same.
* config/rs6000/aix64.opt: Same.
* config/rs6000/darwin.opt: Same.
* config/rs6000/linux64.opt: Same.
* config/rs6000/rs6000.opt: Same.
* config/rs6000/sysv4.opt: Same.
* config/s390/s390.opt: Same.
* config/s390/tpf.opt: Same.
* config/sh/sh.opt: Same.
* config/sol2.opt: Same.
* config/sparc/long-double-switch.opt: Same.
* config/sparc/sparc.opt: Same.
* config/spu/spu.opt: Same.
* config/stormy16/stormy16.opt: Same.
* config/tilegx/tilegx.opt: Same.
* config/tilepro/tilepro.opt: Same.
* config/v850/v850.opt: Same.
* config/vax/vax.opt: Same.
* config/visium/visium.opt: Same.
* config/vms/vms.opt: Same.
* config/vxworks.opt: Same.
* config/xtensa/xtensa.opt: Same.
* fortran/lang.opt: Same.
testsuite/
PR driver/68043
* gcc.misc-tests/help.exp: Adjust.
* lib/options.exp (check_for_options): Add detail to output.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229155 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
74 files changed, 1197 insertions, 1197 deletions
diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index a1ce58d4ea8..c031bcc7be6 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -62,39 +62,39 @@ Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE) mbig-endian Target Report RejectNegative Mask(BIG_END) -Assume target CPU is configured as big endian +Assume target CPU is configured as big endian. mgeneral-regs-only Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save -Generate code which uses only the general registers +Generate code which uses only the general registers. mfix-cortex-a53-835769 Target Report Var(aarch64_fix_a53_err835769) Init(2) Save -Workaround for ARM Cortex-A53 Erratum number 835769 +Workaround for ARM Cortex-A53 Erratum number 835769. mfix-cortex-a53-843419 Target Report -Workaround for ARM Cortex-A53 Erratum number 843419 +Workaround for ARM Cortex-A53 Erratum number 843419. mlittle-endian Target Report RejectNegative InverseMask(BIG_END) -Assume target CPU is configured as little endian +Assume target CPU is configured as little endian. mcmodel= Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_CMODEL_SMALL) Save -Specify the code model +Specify the code model. mstrict-align Target Report RejectNegative Mask(STRICT_ALIGN) Save -Don't assume that unaligned accesses are handled by the system +Don't assume that unaligned accesses are handled by the system. momit-leaf-frame-pointer Target Report Var(flag_omit_leaf_frame_pointer) Init(2) Save -Omit the frame pointer in leaf functions +Omit the frame pointer in leaf functions. mtls-dialect= Target RejectNegative Joined Enum(tls_type) Var(aarch64_tls_dialect) Init(TLS_DESCRIPTORS) Save -Specify TLS dialect +Specify TLS dialect. mtls-size= Target RejectNegative Joined Var(aarch64_tls_size) Enum(aarch64_tls_size) @@ -117,23 +117,23 @@ Enum(aarch64_tls_size) String(48) Value(48) march= Target RejectNegative ToLower Joined Var(aarch64_arch_string) --march=ARCH Use features of architecture ARCH +-march=ARCH Use features of architecture ARCH. mcpu= Target RejectNegative ToLower Joined Var(aarch64_cpu_string) --mcpu=CPU Use features of and optimize for CPU +-mcpu=CPU Use features of and optimize for CPU. mtune= Target RejectNegative ToLower Joined Var(aarch64_tune_string) --mtune=CPU Optimize for CPU +-mtune=CPU Optimize for CPU. mabi= Target RejectNegative Joined Enum(aarch64_abi) Var(aarch64_abi) Init(AARCH64_ABI_DEFAULT) --mabi=ABI Generate code that conforms to the specified ABI +-mabi=ABI Generate code that conforms to the specified ABI. moverride= Target RejectNegative ToLower Joined Var(aarch64_override_tune_string) --moverride=STRING Power users only! Override CPU optimization parameters +-moverride=STRING Power users only! Override CPU optimization parameters. Enum Name(aarch64_abi) Type(int) diff --git a/gcc/config/alpha/alpha.opt b/gcc/config/alpha/alpha.opt index e55f3a53771..08d71371079 100644 --- a/gcc/config/alpha/alpha.opt +++ b/gcc/config/alpha/alpha.opt @@ -20,11 +20,11 @@ msoft-float Target Report Mask(SOFT_FP) -Do not use hardware fp +Do not use hardware fp. mfp-regs Target Report Mask(FPREGS) -Use fp registers +Use fp registers. mgas Target Ignore @@ -32,99 +32,99 @@ Does nothing. Preserved for backward compatibility. mieee-conformant Target RejectNegative Mask(IEEE_CONFORMANT) -Request IEEE-conformant math library routines (OSF/1) +Request IEEE-conformant math library routines (OSF/1). mieee Target Report RejectNegative Mask(IEEE) -Emit IEEE-conformant code, without inexact exceptions +Emit IEEE-conformant code, without inexact exceptions. mieee-with-inexact Target Report RejectNegative Mask(IEEE_WITH_INEXACT) mbuild-constants Target Report Mask(BUILD_CONSTANTS) -Do not emit complex integer constants to read-only memory +Do not emit complex integer constants to read-only memory. mfloat-vax Target Report RejectNegative Mask(FLOAT_VAX) -Use VAX fp +Use VAX fp. mfloat-ieee Target Report RejectNegative InverseMask(FLOAT_VAX) -Do not use VAX fp +Do not use VAX fp. mbwx Target Report Mask(BWX) -Emit code for the byte/word ISA extension +Emit code for the byte/word ISA extension. mmax Target Report Mask(MAX) -Emit code for the motion video ISA extension +Emit code for the motion video ISA extension. mfix Target Report Mask(FIX) -Emit code for the fp move and sqrt ISA extension +Emit code for the fp move and sqrt ISA extension. mcix Target Report Mask(CIX) -Emit code for the counting ISA extension +Emit code for the counting ISA extension. mexplicit-relocs Target Report Mask(EXPLICIT_RELOCS) -Emit code using explicit relocation directives +Emit code using explicit relocation directives. msmall-data Target Report RejectNegative Mask(SMALL_DATA) -Emit 16-bit relocations to the small data areas +Emit 16-bit relocations to the small data areas. mlarge-data Target Report RejectNegative InverseMask(SMALL_DATA) -Emit 32-bit relocations to the small data areas +Emit 32-bit relocations to the small data areas. msmall-text Target Report RejectNegative Mask(SMALL_TEXT) -Emit direct branches to local functions +Emit direct branches to local functions. mlarge-text Target Report RejectNegative InverseMask(SMALL_TEXT) -Emit indirect branches to local functions +Emit indirect branches to local functions. mtls-kernel Target Report Mask(TLS_KERNEL) -Emit rdval instead of rduniq for thread pointer +Emit rdval instead of rduniq for thread pointer. mlong-double-128 Target Report RejectNegative Mask(LONG_DOUBLE_128) -Use 128-bit long double +Use 128-bit long double. mlong-double-64 Target Report RejectNegative InverseMask(LONG_DOUBLE_128) -Use 64-bit long double +Use 64-bit long double. mcpu= Target RejectNegative Joined Var(alpha_cpu_string) -Use features of and schedule given CPU +Use features of and schedule given CPU. mtune= Target RejectNegative Joined Var(alpha_tune_string) -Schedule given CPU +Schedule given CPU. mfp-rounding-mode= Target RejectNegative Joined Var(alpha_fprm_string) -Control the generated fp rounding mode +Control the generated fp rounding mode. mfp-trap-mode= Target RejectNegative Joined Var(alpha_fptm_string) -Control the IEEE trap mode +Control the IEEE trap mode. mtrap-precision= Target RejectNegative Joined Var(alpha_tp_string) -Control the precision given to fp exceptions +Control the precision given to fp exceptions. mmemory-latency= Target RejectNegative Joined Var(alpha_mlat_string) -Tune expected memory latency +Tune expected memory latency. mtls-size= Target RejectNegative Joined UInteger Var(alpha_tls_size) Init(32) -Specify bit size of immediate TLS offsets +Specify bit size of immediate TLS offsets. diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index 7c859e4bfcd..29e89f93d15 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -23,39 +23,39 @@ config/arc/arc-opts.h mbig-endian Target Report RejectNegative Mask(BIG_ENDIAN) -Compile code for big endian mode +Compile code for big endian mode. mlittle-endian Target Report RejectNegative InverseMask(BIG_ENDIAN) -Compile code for little endian mode. This is the default +Compile code for little endian mode. This is the default. mno-cond-exec Target Report RejectNegative Mask(NO_COND_EXEC) -Disable ARCompact specific pass to generate conditional execution instructions +Disable ARCompact specific pass to generate conditional execution instructions. mA6 Target Report -Generate ARCompact 32-bit code for ARC600 processor +Generate ARCompact 32-bit code for ARC600 processor. mARC600 Target Report -Same as -mA6 +Same as -mA6. mARC601 Target Report -Generate ARCompact 32-bit code for ARC601 processor +Generate ARCompact 32-bit code for ARC601 processor. mA7 Target Report -Generate ARCompact 32-bit code for ARC700 processor +Generate ARCompact 32-bit code for ARC700 processor. mARC700 Target Report -Same as -mA7 +Same as -mA7. mmixed-code Target Report Mask(MIXED_CODE_SET) -Tweak register allocation to help 16-bit instruction generation +Tweak register allocation to help 16-bit instruction generation. ; originally this was: ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions ; but we do that without -mmixed-code, too, it's just a different instruction @@ -65,43 +65,43 @@ Tweak register allocation to help 16-bit instruction generation ; actually interesting option, and we want that to have its own comment. mvolatile-cache Target Report RejectNegative Mask(VOLATILE_CACHE_SET) -Use ordinarily cached memory accesses for volatile references +Use ordinarily cached memory accesses for volatile references. mno-volatile-cache Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET) -Enable cache bypass for volatile references +Enable cache bypass for volatile references. mbarrel-shifter Target Report Mask(BARREL_SHIFTER) -Generate instructions supported by barrel shifter +Generate instructions supported by barrel shifter. mnorm Target Report Mask(NORM_SET) -Generate norm instruction +Generate norm instruction. mswap Target Report Mask(SWAP_SET) -Generate swap instruction +Generate swap instruction. mmul64 Target Report Mask(MUL64_SET) -Generate mul64 and mulu64 instructions +Generate mul64 and mulu64 instructions. mno-mpy Target Report Mask(NOMPY_SET) -Do not generate mpy instructions for ARC700 +Do not generate mpy instructions for ARC700. mea Target Report Mask(EA_SET) -Generate Extended arithmetic instructions. Currently only divaw, adds, subs and sat16 are supported +Generate Extended arithmetic instructions. Currently only divaw, adds, subs and sat16 are supported. msoft-float Target Report Mask(0) -Dummy flag. This is the default unless FPX switches are provided explicitly +Dummy flag. This is the default unless FPX switches are provided explicitly. mlong-calls Target Report Mask(LONG_CALLS_SET) -Generate call insns as register indirect calls +Generate call insns as register indirect calls. mno-brcc Target Report Mask(NO_BRCC_SET) @@ -113,7 +113,7 @@ Generate sdata references. This is the default, unless you compile for PIC. mno-millicode Target Report Mask(NO_MILLICODE_THUNK_SET) -Do not generate millicode thunks (needed only with -Os) +Do not generate millicode thunks (needed only with -Os). mspfp Target Report Mask(SPFP_COMPACT_SET) @@ -153,7 +153,7 @@ Enable generation of ARC SIMD instructions via target-specific builtins. mcpu= Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE) --mcpu=CPU Compile code for ARC variant CPU +-mcpu=CPU Compile code for ARC variant CPU. Enum Name(processor_type) Type(enum processor_type) @@ -169,11 +169,11 @@ Enum(processor_type) String(ARC700) Value(PROCESSOR_ARC700) msize-level= Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1) -size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os +size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os. misize Target Report PchIgnore Var(TARGET_DUMPISIZE) -Annotate assembler instructions with estimated addresses +Annotate assembler instructions with estimated addresses. mmultcost= Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1) @@ -205,7 +205,7 @@ Tune for ARC700 R4.2 Cpu with XMAC block. mindexed-loads Target Var(TARGET_INDEXED_LOADS) -Enable the use of indexed loads +Enable the use of indexed loads. mauto-modify-reg Target Var(TARGET_AUTO_MODIFY_REG) @@ -213,13 +213,13 @@ Enable the use of pre/post modify with register displacement. mmul32x16 Target Report Mask(MULMAC_32BY16_SET) -Generate 32x16 multiply and mac instructions +Generate 32x16 multiply and mac instructions. ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) , ; alas, basic-block.h is not included in options.c . munalign-prob-threshold= Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2) -Set probability threshold for unaligning branches +Set probability threshold for unaligning branches. mmedium-calls Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT) @@ -243,11 +243,11 @@ Enable Rcw constraint handling - ccfsm condexec mostly depends on this. mearly-cbranchsi Target Var(TARGET_EARLY_CBRANCHSI) -Enable pre-reload use of cbranchsi pattern +Enable pre-reload use of cbranchsi pattern. mbbit-peephole Target Var(TARGET_BBIT_PEEPHOLE) -Enable bbit peephole2 +Enable bbit peephole2. mcase-vector-pcrel Target Var(TARGET_CASE_VECTOR_PC_RELATIVE) @@ -255,7 +255,7 @@ Use pc-relative switch case tables - this enables case table shortening. mcompact-casesi Target Var(TARGET_COMPACT_CASESI) -Enable compact casesi pattern +Enable compact casesi pattern. mq-class Target Var(TARGET_Q_CLASS) @@ -270,15 +270,15 @@ Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc. ; macro symbols as well. mcrc Target Report -Enable variable polynomial CRC extension +Enable variable polynomial CRC extension. mdsp-packa Target Report -Enable DSP 3.1 Pack A extensions +Enable DSP 3.1 Pack A extensions. mdvbf Target Report -Enable dual viterbi butterfly extension +Enable dual viterbi butterfly extension. mmac-d16 Target Report Undocumented @@ -288,24 +288,24 @@ Target Report Undocumented mtelephony Target Report RejectNegative -Enable Dual and Single Operand Instructions for Telephony +Enable Dual and Single Operand Instructions for Telephony. mxy Target Report -Enable XY Memory extension (DSP version 3) +Enable XY Memory extension (DSP version 3). ; ARC700 4.10 extension instructions mlock Target Report -Enable Locked Load/Store Conditional extension +Enable Locked Load/Store Conditional extension. mswape Target Report -Enable swap byte ordering extension instruction +Enable swap byte ordering extension instruction. mrtsc Target Report -Enable 64-bit Time-Stamp Counter extension instruction +Enable 64-bit Time-Stamp Counter extension instruction. mno-epilogue-cfi Target Report RejectNegative InverseMask(EPILOGUE_CFI) @@ -337,23 +337,23 @@ Pass -marclinux_prof option through to linker. ; so don't enable by default. mlra Target Mask(LRA) -Enable lra +Enable lra. mlra-priority-none Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE) -Don't indicate any priority with TARGET_REGISTER_PRIORITY +Don't indicate any priority with TARGET_REGISTER_PRIORITY. mlra-priority-compact Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT) -Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY +Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY. mlra-priority-noncompact Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT) -Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY +Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY. mucb-mcount Target Report Var(TARGET_UCB_MCOUNT) -instrument with mcount calls as in the ucb code +instrument with mcount calls as in the ucb code. ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index c9095b9eeab..666ff732264 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -33,7 +33,7 @@ Enum(tls_type) String(gnu2) Value(TLS_GNU2) mabi= Target RejectNegative Joined Enum(arm_abi_type) Var(arm_abi) Init(ARM_DEFAULT_ABI) -Specify an ABI +Specify an ABI. Enum Name(arm_abi_type) Type(enum arm_abi_type) @@ -56,29 +56,29 @@ Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX) mabort-on-noreturn Target Report Mask(ABORT_NORETURN) -Generate a call to abort if a noreturn function returns +Generate a call to abort if a noreturn function returns. mapcs Target RejectNegative Mask(APCS_FRAME) Undocumented mapcs-float Target Report Mask(APCS_FLOAT) -Pass FP arguments in FP registers +Pass FP arguments in FP registers. mapcs-frame Target Report Mask(APCS_FRAME) -Generate APCS conformant stack frames +Generate APCS conformant stack frames. mapcs-reentrant Target Report Mask(APCS_REENT) -Generate re-entrant, PIC code +Generate re-entrant, PIC code. mapcs-stack-check Target Report Mask(APCS_STACK) Undocumented march= Target RejectNegative ToLower Joined Enum(arm_arch) Var(arm_arch_option) -Specify the name of the target architecture +Specify the name of the target architecture. ; Other arm_arch values are loaded from arm-tables.opt ; but that is a generated file and this is an odd-one-out. @@ -91,23 +91,23 @@ Generate code in 32 bit ARM state. mbig-endian Target Report RejectNegative Mask(BIG_END) -Assume target CPU is configured as big endian +Assume target CPU is configured as big endian. mcallee-super-interworking Target Report Mask(CALLEE_INTERWORKING) -Thumb: Assume non-static functions may be called from ARM code +Thumb: Assume non-static functions may be called from ARM code. mcaller-super-interworking Target Report Mask(CALLER_INTERWORKING) -Thumb: Assume function pointers may go to non-Thumb aware code +Thumb: Assume function pointers may go to non-Thumb aware code. mcpu= Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_cpu_option) Init(arm_none) -Specify the name of the target CPU +Specify the name of the target CPU. mfloat-abi= Target RejectNegative Joined Enum(float_abi_type) Var(arm_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI) -Specify if floating point hardware should be used +Specify if floating point hardware should be used. Enum Name(float_abi_type) Type(enum float_abi_type) @@ -124,11 +124,11 @@ Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD) mflip-thumb Target Report Var(TARGET_FLIP_THUMB) Undocumented -Switch ARM/Thumb modes on alternating functions for compiler testing +Switch ARM/Thumb modes on alternating functions for compiler testing. mfp16-format= Target RejectNegative Joined Enum(arm_fp16_format_type) Var(arm_fp16_format) Init(ARM_FP16_FORMAT_NONE) -Specify the __fp16 floating-point format +Specify the __fp16 floating-point format. Enum Name(arm_fp16_format_type) Type(enum arm_fp16_format_type) @@ -145,18 +145,18 @@ Enum(arm_fp16_format_type) String(alternative) Value(ARM_FP16_FORMAT_ALTERNATIVE mfpu= Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index) -Specify the name of the target floating point hardware/format +Specify the name of the target floating point hardware/format. mhard-float Target RejectNegative Alias(mfloat-abi=, hard) Undocumented mlittle-endian Target Report RejectNegative InverseMask(BIG_END) -Assume target CPU is configured as little endian +Assume target CPU is configured as little endian. mlong-calls Target Report Mask(LONG_CALLS) -Generate call insns as indirect calls, if necessary +Generate call insns as indirect calls, if necessary. mpic-data-is-text-relative Target Report Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) @@ -164,42 +164,42 @@ Assume data segments are relative to text segment. mpic-register= Target RejectNegative Joined Var(arm_pic_register_string) -Specify the register to be used for PIC addressing +Specify the register to be used for PIC addressing. mpoke-function-name Target Report Mask(POKE_FUNCTION_NAME) -Store function names in object code +Store function names in object code. msched-prolog Target Report Mask(SCHED_PROLOG) -Permit scheduling of a function's prologue sequence +Permit scheduling of a function's prologue sequence. msingle-pic-base Target Report Mask(SINGLE_PIC_BASE) -Do not load the PIC register in function prologues +Do not load the PIC register in function prologues. msoft-float Target RejectNegative Alias(mfloat-abi=, soft) Undocumented mstructure-size-boundary= Target RejectNegative Joined UInteger Var(arm_structure_size_boundary) Init(DEFAULT_STRUCTURE_SIZE_BOUNDARY) -Specify the minimum bit alignment of structures +Specify the minimum bit alignment of structures. mthumb Target Report RejectNegative Mask(THUMB) Save -Generate code for Thumb state +Generate code for Thumb state. mthumb-interwork Target Report Mask(INTERWORK) -Support calls between Thumb and ARM instruction sets +Support calls between Thumb and ARM instruction sets. mtls-dialect= Target RejectNegative Joined Enum(tls_type) Var(target_tls_dialect) Init(TLS_GNU) -Specify thread local storage scheme +Specify thread local storage scheme. mtp= Target RejectNegative Joined Enum(arm_tp_type) Var(target_thread_pointer) Init(TP_AUTO) -Specify how to access the thread pointer +Specify how to access the thread pointer. Enum Name(arm_tp_type) Type(enum arm_tp_type) @@ -216,15 +216,15 @@ Enum(arm_tp_type) String(cp15) Value(TP_CP15) mtpcs-frame Target Report Mask(TPCS_FRAME) -Thumb: Generate (non-leaf) stack frames even if not needed +Thumb: Generate (non-leaf) stack frames even if not needed. mtpcs-leaf-frame Target Report Mask(TPCS_LEAF_FRAME) -Thumb: Generate (leaf) stack frames even if not needed +Thumb: Generate (leaf) stack frames even if not needed. mtune= Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_tune_option) Init(arm_none) -Tune code for the given processor +Tune code for the given processor. mprint-tune-info Target Report RejectNegative Var(print_tune_info) Init(0) @@ -239,11 +239,11 @@ Enum(processor_type) String(native) Value(-1) DriverOnly mvectorize-with-neon-quad Target Report RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE) -Use Neon quad-word (rather than double-word) registers for vectorization +Use Neon quad-word (rather than double-word) registers for vectorization. mvectorize-with-neon-double Target Report RejectNegative Mask(NEON_VECTORIZE_DOUBLE) -Use Neon double-word (rather than quad-word) registers for vectorization +Use Neon double-word (rather than quad-word) registers for vectorization. mword-relocations Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) diff --git a/gcc/config/avr/avr.opt b/gcc/config/avr/avr.opt index 7e32ce5a350..86245768064 100644 --- a/gcc/config/avr/avr.opt +++ b/gcc/config/avr/avr.opt @@ -20,23 +20,23 @@ mcall-prologues Target Report Mask(CALL_PROLOGUES) -Use subroutines for function prologues and epilogues +Use subroutines for function prologues and epilogues. mmcu= Target RejectNegative Joined Var(avr_mmcu) MissingArgError(missing device or architecture after %qs) --mmcu=MCU Select the target MCU +-mmcu=MCU Select the target MCU. mn-flash= Target RejectNegative Joined Var(avr_n_flash) UInteger Init(-1) -Set the number of 64 KiB flash segments +Set the number of 64 KiB flash segments. mskip-bug Target Report Mask(SKIP_BUG) -Indicate presence of a processor erratum +Indicate presence of a processor erratum. mrmw Target Report Mask(RMW) -Enable Read-Modify-Write (RMW) instructions support/use +Enable Read-Modify-Write (RMW) instructions support/use. mdeb Target Report Undocumented Mask(ALL_DEBUG) @@ -46,11 +46,11 @@ Target RejectNegative Joined Undocumented Var(avr_log_details) mint8 Target Report Mask(INT8) -Use an 8-bit 'int' type +Use an 8-bit 'int' type. mno-interrupts Target Report RejectNegative Mask(NO_INTERRUPTS) -Change the stack pointer without disabling interrupts +Change the stack pointer without disabling interrupts. mbranch-cost= Target Report Joined RejectNegative UInteger Var(avr_branch_cost) Init(0) @@ -64,11 +64,11 @@ Target Report Undocumented Mask(ORDER_2) mtiny-stack Target Report Mask(TINY_STACK) -Change only the low 8 bits of the stack pointer +Change only the low 8 bits of the stack pointer. mrelax Target Report -Relax branches +Relax branches. mpmem-wrap-around Target Report @@ -93,8 +93,8 @@ Warn if the address space of an address is changed. mfract-convert-truncate Target Report Mask(FRACT_CONV_TRUNC) -Allow to use truncation instead of rounding towards 0 for fractional int types +Allow to use truncation instead of rounding towards 0 for fractional int types. nodevicelib Driver Target Report RejectNegative -Do not link against the device-specific library lib<MCU>.a +Do not link against the device-specific library lib<MCU>.a. diff --git a/gcc/config/bfin/bfin.opt b/gcc/config/bfin/bfin.opt index cbc5c9e8c7b..bf7ad5b0886 100644 --- a/gcc/config/bfin/bfin.opt +++ b/gcc/config/bfin/bfin.opt @@ -37,19 +37,19 @@ unsigned int bfin_workarounds = 0 msim Target RejectNegative -Use simulator runtime +Use simulator runtime. mcpu= Target RejectNegative Joined -Specify the name of the target CPU +Specify the name of the target CPU. momit-leaf-frame-pointer Target Report Mask(OMIT_LEAF_FRAME_POINTER) -Omit frame pointer for leaf functions +Omit frame pointer for leaf functions. mlow64k Target Report Mask(LOW_64K) -Program is entirely located in low 64k of memory +Program is entirely located in low 64k of memory. mcsync-anomaly Target Report Var(bfin_csync_anomaly) Init(-1) @@ -62,7 +62,7 @@ Avoid speculative loads to work around a hardware anomaly. mid-shared-library Target Report Mask(ID_SHARED_LIBRARY) -Enabled ID based shared library +Enabled ID based shared library. mleaf-id-shared-library Target Report Mask(LEAF_ID_SHARED_LIBRARY) @@ -71,47 +71,47 @@ but may be used as a shared library. mshared-library-id= Target RejectNegative Joined UInteger Var(bfin_library_id) -ID of shared library to build +ID of shared library to build. msep-data Target Report Mask(SEP_DATA) -Enable separate data segment +Enable separate data segment. mlong-calls Target Report Mask(LONG_CALLS) -Avoid generating pc-relative calls; use indirection +Avoid generating pc-relative calls; use indirection. mfast-fp Target Report Mask(FAST_FP) -Link with the fast floating-point library +Link with the fast floating-point library. mfdpic Target Report Mask(FDPIC) -Enable Function Descriptor PIC mode +Enable Function Descriptor PIC mode. minline-plt Target Report Mask(INLINE_PLT) -Enable inlining of PLT in function calls +Enable inlining of PLT in function calls. mstack-check-l1 Target Report Mask(STACK_CHECK_L1) -Do stack checking using bounds in L1 scratch memory +Do stack checking using bounds in L1 scratch memory. mmulticore Target Report Mask(MULTICORE) -Enable multicore support +Enable multicore support. mcorea Target Report Mask(COREA) -Build for Core A +Build for Core A. mcoreb Target Report Mask(COREB) -Build for Core B +Build for Core B. msdram Target Report Mask(SDRAM) -Build for SDRAM +Build for SDRAM. micplb Target Report Mask(ICPLB) diff --git a/gcc/config/c6x/c6x.opt b/gcc/config/c6x/c6x.opt index 56877af5bf0..72fd8fb6dad 100644 --- a/gcc/config/c6x/c6x.opt +++ b/gcc/config/c6x/c6x.opt @@ -27,23 +27,23 @@ config/c6x/c6x-opts.h mbig-endian Target Report RejectNegative Mask(BIG_ENDIAN) -Use big-endian byte order +Use big-endian byte order. mlittle-endian Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN) -Use little-endian byte order +Use little-endian byte order. msim Target RejectNegative -Use simulator runtime +Use simulator runtime. msdata= Target RejectNegative Enum(c6x_sdata) Joined Var(c6x_sdata_mode) Init(C6X_SDATA_DEFAULT) -Select method for sdata handling +Select method for sdata handling. Enum Name(c6x_sdata) Type(enum c6x_sdata) -Valid arguments for the -msdata= option +Valid arguments for the -msdata= option. EnumValue Enum(c6x_sdata) String(none) Value(C6X_SDATA_NONE) @@ -56,12 +56,12 @@ Enum(c6x_sdata) String(all) Value(C6X_SDATA_ALL) mdsbt Target Mask(DSBT) -Compile for the DSBT shared library ABI +Compile for the DSBT shared library ABI. mlong-calls Target Report Mask(LONG_CALLS) -Avoid generating pc-relative calls; use indirection +Avoid generating pc-relative calls; use indirection. march= Target RejectNegative Joined Enum(c6x_isa) Var(c6x_arch_option) -Specify the name of the target architecture +Specify the name of the target architecture. diff --git a/gcc/config/cr16/cr16.opt b/gcc/config/cr16/cr16.opt index ff43868d267..02d8609e914 100644 --- a/gcc/config/cr16/cr16.opt +++ b/gcc/config/cr16/cr16.opt @@ -20,30 +20,30 @@ msim Target --msim Use simulator runtime +-msim Use simulator runtime. mbit-ops Target Report Mask(BIT_OPS) -Generate SBIT, CBIT instructions +Generate SBIT, CBIT instructions. mmac Target Report Mask(MAC) -Support multiply accumulate instructions +Support multiply accumulate instructions. mdebug-addr Target RejectNegative Var(TARGET_DEBUG_ADDR) Undocumented mdata-model= Target RejectNegative JoinedOrMissing Var(cr16_data_model) -Treat data references as near, far or medium. medium is default +Treat data references as near, far or medium. medium is default. mcr16c Target RejectNegative Mask(CR16C) -Generate code for CR16C architecture +Generate code for CR16C architecture. mcr16cplus Target RejectNegative InverseMask(CR16C,CR16CP) -Generate code for CR16C+ architecture (Default) +Generate code for CR16C+ architecture (Default). mint32 Target RejectNegative Mask(INT32) diff --git a/gcc/config/cris/cris.opt b/gcc/config/cris/cris.opt index 5acda39900f..63f8a779068 100644 --- a/gcc/config/cris/cris.opt +++ b/gcc/config/cris/cris.opt @@ -42,18 +42,18 @@ ; on the same page, including the TLB registers). mmul-bug-workaround Target Report Mask(MUL_BUG) -Work around bug in multiplication instruction +Work around bug in multiplication instruction. ; TARGET_ETRAX4_ADD: Instruction-set additions from Etrax 4 and up. ; (Just "lz".) metrax4 Target Report Mask(ETRAX4_ADD) -Compile for ETRAX 4 (CRIS v3) +Compile for ETRAX 4 (CRIS v3). ; See cris_handle_option. metrax100 Target Report RejectNegative -Compile for ETRAX 100 (CRIS v8) +Compile for ETRAX 100 (CRIS v8). ; See cris_handle_option. mno-etrax100 @@ -61,14 +61,14 @@ Target Report RejectNegative Undocumented mpdebug Target Report Mask(PDEBUG) -Emit verbose debug information in assembly code +Emit verbose debug information in assembly code. ; TARGET_CCINIT: Whether to use condition-codes generated by ; insns other than the immediately preceding compare/test insn. ; Used to check for errors in notice_update_cc. mcc-init Target Report Mask(CCINIT) -Do not use condition codes from normal instructions +Do not use condition codes from normal instructions. ; TARGET_SIDE_EFFECT_PREFIXES: Whether to use side-effect ; patterns. Used to debug the [rx=ry+i] type patterns. @@ -77,7 +77,7 @@ Target Report RejectNegative Mask(SIDE_EFFECT_PREFIXES) Undocumented mno-side-effects Target Report RejectNegative InverseMask(SIDE_EFFECT_PREFIXES) -Do not emit addressing modes with side-effect assignment +Do not emit addressing modes with side-effect assignment. ; TARGET_STACK_ALIGN: Whether to *keep* (not force) alignment of ; stack at 16 (or 32, depending on TARGET_ALIGN_BY_32) bits. @@ -86,7 +86,7 @@ Target Report RejectNegative Mask(STACK_ALIGN) Undocumented mno-stack-align Target Report RejectNegative InverseMask(STACK_ALIGN) -Do not tune stack alignment +Do not tune stack alignment. ; TARGET_DATA_ALIGN: Whether to do alignment on individual ; modifiable objects. @@ -95,7 +95,7 @@ Target Report RejectNegative Mask(DATA_ALIGN) Undocumented mno-data-align Target Report RejectNegative InverseMask(DATA_ALIGN) -Do not tune writable data alignment +Do not tune writable data alignment. ; TARGET_CONST_ALIGN: Whether to do alignment on individual ; non-modifiable objects. @@ -104,7 +104,7 @@ Target Report RejectNegative Mask(CONST_ALIGN) Undocumented mno-const-align Target Report RejectNegative InverseMask(CONST_ALIGN) -Do not tune code and read-only data alignment +Do not tune code and read-only data alignment. ; See cris_handle_option. m32-bit @@ -113,7 +113,7 @@ Target Report RejectNegative Undocumented ; See cris_handle_option. m32bit Target Report RejectNegative -Align code and data to 32 bits +Align code and data to 32 bits. ; See cris_handle_option. m16-bit @@ -130,7 +130,7 @@ Target Report RejectNegative Undocumented ; See cris_handle_option. m8bit Target Report RejectNegative -Don't align items in code or data +Don't align items in code or data. ; TARGET_PROLOGUE_EPILOGUE: Whether or not to omit function ; prologue and epilogue. @@ -139,14 +139,14 @@ Target Report RejectNegative Mask(PROLOGUE_EPILOGUE) Undocumented mno-prologue-epilogue Target Report RejectNegative InverseMask(PROLOGUE_EPILOGUE) -Do not emit function prologue or epilogue +Do not emit function prologue or epilogue. ; We have to handle this m-option here since we can't wash it ; off in both CC1_SPEC and CC1PLUS_SPEC. mbest-lib-options Target Report RejectNegative -Use the most feature-enabling options allowed by other options +Use the most feature-enabling options allowed by other options. ; FIXME: The following comment relates to gcc before cris.opt. ; Check if it's still valid: @@ -155,22 +155,22 @@ Use the most feature-enabling options allowed by other options ; Kludgy, but needed for some multilibbed files. moverride-best-lib-options Target Report RejectNegative -Override -mbest-lib-options +Override -mbest-lib-options. mcpu= Target Report RejectNegative Joined Undocumented Var(cris_cpu_str) march= Target Report RejectNegative Joined Var(cris_cpu_str) --march=ARCH Generate code for the specified chip or CPU version +-march=ARCH Generate code for the specified chip or CPU version. mtune= Target Report RejectNegative Joined Var(cris_tune_str) --mtune=ARCH Tune alignment for the specified chip or CPU version +-mtune=ARCH Tune alignment for the specified chip or CPU version. mmax-stackframe= Target Report RejectNegative Joined Var(cris_max_stackframe_str) --mmax-stackframe=SIZE Warn when a stackframe is larger than the specified size +-mmax-stackframe=SIZE Warn when a stackframe is larger than the specified size. max-stackframe= Target Report RejectNegative Joined Undocumented Var(cris_max_stackframe_str) @@ -181,7 +181,7 @@ Emit traps as \"break 8\", default for CRIS v3 and up. If disabled, calls to ab mtrap-unaligned-atomic Target Report Var(cris_trap_unaligned_atomic) Init(2) -Emit checks causing \"break 8\" instructions to execute when applying atomic builtins on misaligned memory +Emit checks causing \"break 8\" instructions to execute when applying atomic builtins on misaligned memory. munaligned-atomic-may-use-library Target Report Var(cris_atomics_calling_libfunc) Init(2) diff --git a/gcc/config/cris/linux.opt b/gcc/config/cris/linux.opt index 5283ea6e7c0..84ee07457b2 100644 --- a/gcc/config/cris/linux.opt +++ b/gcc/config/cris/linux.opt @@ -24,7 +24,7 @@ Target Report RejectNegative Undocumented mno-gotplt Target Report RejectNegative Mask(AVOID_GOTPLT) -Together with -fpic and -fPIC, do not use GOTPLT references +Together with -fpic and -fPIC, do not use GOTPLT references. ; There's a small added setup cost with using GOTPLT references ; for the first (resolving) call, but should in total be a win diff --git a/gcc/config/darwin.opt b/gcc/config/darwin.opt index eb1afe73786..518a6d14901 100644 --- a/gcc/config/darwin.opt +++ b/gcc/config/darwin.opt @@ -111,7 +111,7 @@ Driver mconstant-cfstrings Target Report Var(darwin_constant_cfstrings) Init(1) -Generate compile-time CFString objects +Generate compile-time CFString objects. multi_module Driver RejectNegative Alias(Zmulti_module) @@ -208,20 +208,20 @@ Driver Wnonportable-cfstrings Target Report Var(darwin_warn_nonportable_cfstrings) Init(1) Warning -Warn if constant CFString objects contain non-portable characters +Warn if constant CFString objects contain non-portable characters. ; Use new-style pic stubs if this is true, x86 only so far. matt-stubs Target Report Var(darwin_macho_att_stub) Init(1) -Generate AT&T-style stubs for Mach-O +Generate AT&T-style stubs for Mach-O. mdynamic-no-pic Target Common Report Mask(MACHO_DYNAMIC_NO_PIC) -Generate code suitable for executables (NOT shared libs) +Generate code suitable for executables (NOT shared libs). mfix-and-continue Target Report Var(darwin_fix_and_continue) -Generate code suitable for fast turn around debugging +Generate code suitable for fast turn around debugging. ; The Init here is for the convenience of GCC developers, so that cc1 ; and cc1plus don't crash if no -mmacosx-version-min is passed. The @@ -229,23 +229,23 @@ Generate code suitable for fast turn around debugging ; Init is never used. mmacosx-version-min= Target Joined Report Var(darwin_macosx_version_min) Init(DEF_MIN_OSX_VERSION) -The earliest MacOS X version on which this program will run +The earliest MacOS X version on which this program will run. mone-byte-bool Target RejectNegative Report Var(darwin_one_byte_bool) -Set sizeof(bool) to 1 +Set sizeof(bool) to 1. fapple-kext Target Report C++ Var(flag_apple_kext) -Generate code for darwin loadable kernel extensions +Generate code for darwin loadable kernel extensions. mkernel Target Report Var(flag_mkernel) -Generate code for the kernel or loadable kernel extensions +Generate code for the kernel or loadable kernel extensions. iframework Target RejectNegative C ObjC C++ ObjC++ Joined Separate --iframework <dir> Add <dir> to the end of the system framework include path +-iframework <dir> Add <dir> to the end of the system framework include path. X Driver diff --git a/gcc/config/epiphany/epiphany.opt b/gcc/config/epiphany/epiphany.opt index e2deed6db04..297ceb81a39 100644 --- a/gcc/config/epiphany/epiphany.opt +++ b/gcc/config/epiphany/epiphany.opt @@ -29,7 +29,7 @@ preferentially allocate registers that allow short instruction generation. mbranch-cost= Target RejectNegative Joined UInteger Var(epiphany_branch_cost) Init(3) -Set branch cost +Set branch cost. mcmove Target Mask(CMOVE) @@ -37,7 +37,7 @@ enable conditional move instruction usage. mnops= Target RejectNegative Joined UInteger Var(epiphany_n_nops) Init(0) -set number of nops to emit before each insn pattern +set number of nops to emit before each insn pattern. ; Problems with using the flags from fsub for comparison are: ; - Because of underflow (lack of subnormal numbers), different small numbers @@ -49,19 +49,19 @@ set number of nops to emit before each insn pattern ; equal. msoft-cmpsf Target Mask(SOFT_CMPSF) -Use software floating point comparisons +Use software floating point comparisons. msplit-lohi Target Mask(SPLIT_LOHI) -Enable split of 32 bit immediate loads into low / high part +Enable split of 32 bit immediate loads into low / high part. mpost-inc Target Mask(POST_INC) -Enable use of POST_INC / POST_DEC +Enable use of POST_INC / POST_DEC. mpost-modify Target Mask(POST_MODIFY) -Enable use of POST_MODIFY +Enable use of POST_MODIFY. mstack-offset= Target RejectNegative Joined UInteger Var(epiphany_stack_offset) Init(EPIPHANY_STACK_OFFSET) @@ -73,11 +73,11 @@ Assume round to nearest is selected for purposes of scheduling. mlong-calls Target Mask(LONG_CALLS) -Generate call insns as indirect calls +Generate call insns as indirect calls. mshort-calls Target Mask(SHORT_CALLS) -Generate call insns as direct calls +Generate call insns as direct calls. msmall16 Target Mask(SMALL16) @@ -105,7 +105,7 @@ Enum(attr_fp_mode) String(int) Value(FP_MODE_INT) may-round-for-trunc Target Mask(MAY_ROUND_FOR_TRUNC) -A floatig point to integer truncation may be replaced with rounding to save mode switching +A floatig point to integer truncation may be replaced with rounding to save mode switching. mvect-double Target Mask(VECT_DOUBLE) diff --git a/gcc/config/fr30/fr30.opt b/gcc/config/fr30/fr30.opt index 095a0bf4f2d..5a46014f2d9 100644 --- a/gcc/config/fr30/fr30.opt +++ b/gcc/config/fr30/fr30.opt @@ -20,8 +20,8 @@ msmall-model Target Report Mask(SMALL_MODEL) -Assume small address space +Assume small address space. mno-lsim Target RejectNegative -Assume that run-time support has been provided, so omit -lsim from the linker command line +Assume that run-time support has been provided, so omit -lsim from the linker command line. diff --git a/gcc/config/frv/frv.opt b/gcc/config/frv/frv.opt index 9816a8f1b2a..7a8659d243c 100644 --- a/gcc/config/frv/frv.opt +++ b/gcc/config/frv/frv.opt @@ -27,46 +27,46 @@ frv_cpu_t frv_cpu_type = CPU_TYPE macc-4 Target Report RejectNegative Mask(ACC_4) -Use 4 media accumulators +Use 4 media accumulators. macc-8 Target Report RejectNegative InverseMask(ACC_4, ACC_8) -Use 8 media accumulators +Use 8 media accumulators. malign-labels Target Report Mask(ALIGN_LABELS) -Enable label alignment optimizations +Enable label alignment optimizations. malloc-cc Target Report RejectNegative Mask(ALLOC_CC) -Dynamically allocate cc registers +Dynamically allocate cc registers. ; We used to default the branch cost to 2, but it was changed it to 1 to avoid ; generating SCC instructions and or/and-ing them together, and then doing the ; branch on the result, which collectively generate much worse code. mbranch-cost= Target RejectNegative Joined UInteger Var(frv_branch_cost_int) Init(1) -Set the cost of branches +Set the cost of branches. mcond-exec Target Report Mask(COND_EXEC) -Enable conditional execution other than moves/scc +Enable conditional execution other than moves/scc. mcond-exec-insns= Target RejectNegative Joined UInteger Var(frv_condexec_insns) Init(8) -Change the maximum length of conditionally-executed sequences +Change the maximum length of conditionally-executed sequences. mcond-exec-temps= Target RejectNegative Joined UInteger Var(frv_condexec_temps) Init(4) -Change the number of temporary registers that are available to conditionally-executed sequences +Change the number of temporary registers that are available to conditionally-executed sequences. mcond-move Target Report Mask(COND_MOVE) -Enable conditional moves +Enable conditional moves. mcpu= Target RejectNegative Joined Enum(frv_cpu) Var(frv_cpu_type) -Set the target CPU type +Set the target CPU type. Enum Name(frv_cpu) Type(frv_cpu_t) @@ -119,119 +119,119 @@ Target Undocumented Var(TARGET_DEBUG_STACK) mdouble Target Report Mask(DOUBLE) -Use fp double instructions +Use fp double instructions. mdword Target Report Mask(DWORD) -Change the ABI to allow double word insns +Change the ABI to allow double word insns. mfdpic Target Report Mask(FDPIC) -Enable Function Descriptor PIC mode +Enable Function Descriptor PIC mode. mfixed-cc Target Report RejectNegative InverseMask(ALLOC_CC, FIXED_CC) -Just use icc0/fcc0 +Just use icc0/fcc0. mfpr-32 Target Report RejectNegative Mask(FPR_32) -Only use 32 FPRs +Only use 32 FPRs. mfpr-64 Target Report RejectNegative InverseMask(FPR_32, FPR_64) -Use 64 FPRs +Use 64 FPRs. mgpr-32 Target Report RejectNegative Mask(GPR_32) -Only use 32 GPRs +Only use 32 GPRs. mgpr-64 Target Report RejectNegative InverseMask(GPR_32, GPR_64) -Use 64 GPRs +Use 64 GPRs. mgprel-ro Target Report Mask(GPREL_RO) -Enable use of GPREL for read-only data in FDPIC +Enable use of GPREL for read-only data in FDPIC. mhard-float Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) -Use hardware floating point +Use hardware floating point. minline-plt Target Report Mask(INLINE_PLT) -Enable inlining of PLT in function calls +Enable inlining of PLT in function calls. mlibrary-pic Target Report Mask(LIBPIC) -Enable PIC support for building libraries +Enable PIC support for building libraries. mlinked-fp Target Report Mask(LINKED_FP) -Follow the EABI linkage requirements +Follow the EABI linkage requirements. mlong-calls Target Report Mask(LONG_CALLS) -Disallow direct calls to global functions +Disallow direct calls to global functions. mmedia Target Report Mask(MEDIA) -Use media instructions +Use media instructions. mmuladd Target Report Mask(MULADD) -Use multiply add/subtract instructions +Use multiply add/subtract instructions. mmulti-cond-exec Target Report Mask(MULTI_CE) -Enable optimizing &&/|| in conditional execution +Enable optimizing &&/|| in conditional execution. mnested-cond-exec Target Report Mask(NESTED_CE) -Enable nested conditional execution optimizations +Enable nested conditional execution optimizations. ; Not used by the compiler proper. mno-eflags Target RejectNegative -Do not mark ABI switches in e_flags +Do not mark ABI switches in e_flags. moptimize-membar Target Report Mask(OPTIMIZE_MEMBAR) -Remove redundant membars +Remove redundant membars. mpack Target Report Mask(PACK) -Pack VLIW instructions +Pack VLIW instructions. mscc Target Report Mask(SCC) -Enable setting GPRs to the result of comparisons +Enable setting GPRs to the result of comparisons. msched-lookahead= Target RejectNegative Joined UInteger Var(frv_sched_lookahead) Init(4) -Change the amount of scheduler lookahead +Change the amount of scheduler lookahead. msoft-float Target Report RejectNegative Mask(SOFT_FLOAT) -Use software floating point +Use software floating point. mTLS Target Report RejectNegative Mask(BIG_TLS) -Assume a large TLS segment +Assume a large TLS segment. mtls Target Report RejectNegative InverseMask(BIG_TLS) -Do not assume a large TLS segment +Do not assume a large TLS segment. ; Not used by the compiler proper. mtomcat-stats Target -Cause gas to print tomcat statistics +Cause gas to print tomcat statistics. ; Not used by the compiler proper. multilib-library-pic Target RejectNegative -Link with the library-pic libraries +Link with the library-pic libraries. mvliw-branch Target Report Mask(VLIW_BRANCH) -Allow branches to be packed with other instructions +Allow branches to be packed with other instructions. diff --git a/gcc/config/ft32/ft32.opt b/gcc/config/ft32/ft32.opt index 00816ec6a5a..b9b7797c094 100644 --- a/gcc/config/ft32/ft32.opt +++ b/gcc/config/ft32/ft32.opt @@ -20,8 +20,8 @@ msim Target Report Mask(SIM) -target the software simulator +target the software simulator. mlra Target Report Var(ft32_lra_flag) Init(0) Save -Use LRA instead of reload +Use LRA instead of reload. diff --git a/gcc/config/g.opt b/gcc/config/g.opt index a7832df4e71..993dfa4dd92 100644 --- a/gcc/config/g.opt +++ b/gcc/config/g.opt @@ -24,6 +24,6 @@ G Target Joined Separate UInteger Var(g_switch_value) --G<number> Put global and static data smaller than <number> bytes into a special section (on some targets) +-G<number> Put global and static data smaller than <number> bytes into a special section (on some targets). ; This comment is to ensure we retain the blank line above. diff --git a/gcc/config/h8300/h8300.opt b/gcc/config/h8300/h8300.opt index 542c5e8704e..24ba66257bb 100644 --- a/gcc/config/h8300/h8300.opt +++ b/gcc/config/h8300/h8300.opt @@ -20,52 +20,52 @@ ms Target Mask(H8300S_1) -Generate H8S code +Generate H8S code. msx Target Mask(H8300SX) -Generate H8SX code +Generate H8SX code. ms2600 Target Mask(MAC) -Generate H8S/2600 code +Generate H8S/2600 code. mint32 Target RejectNegative Mask(INT32) -Make integers 32 bits wide +Make integers 32 bits wide. maddresses Target Undocumented RejectNegative Mask(ADDRESSES) mquickcall Target Mask(QUICKCALL) -Use registers for argument passing +Use registers for argument passing. mslowbyte Target RejectNegative Mask(SLOWBYTE) -Consider access to byte sized memory slow +Consider access to byte sized memory slow. mrelax Target RejectNegative Mask(RELAX) -Enable linker relaxing +Enable linker relaxing. mh Target Mask(H8300H) -Generate H8/300H code +Generate H8/300H code. mn Target Mask(NORMAL_MODE) -Enable the normal mode +Enable the normal mode. malign-300 Target RejectNegative Mask(ALIGN_300) -Use H8/300 alignment rules +Use H8/300 alignment rules. mexr Target Mask(EXR) -Push extended registers on stack in monitor functions +Push extended registers on stack in monitor functions. mno-exr Target Mask(NEXR) -Do not push extended registers on stack in monitor functions +Do not push extended registers on stack in monitor functions. diff --git a/gcc/config/i386/cygming.opt b/gcc/config/i386/cygming.opt index c7e398f04ce..d9c1259e69c 100644 --- a/gcc/config/i386/cygming.opt +++ b/gcc/config/i386/cygming.opt @@ -20,35 +20,35 @@ mconsole Target RejectNegative -Create console application +Create console application. mdll Target RejectNegative -Generate code for a DLL +Generate code for a DLL. mnop-fun-dllimport Target Report Var(TARGET_NOP_FUN_DLLIMPORT) -Ignore dllimport for functions +Ignore dllimport for functions. mthreads Target RejectNegative -Use Mingw-specific thread support +Use Mingw-specific thread support. mwin32 Target -Set Windows defines +Set Windows defines. mwindows Target -Create GUI application +Create GUI application. mpe-aligned-commons Target Var(use_pe_aligned_common) Init(HAVE_GAS_ALIGNED_COMM) -Use the GNU extension to the PE format for aligned common data +Use the GNU extension to the PE format for aligned common data. muse-libstdc-wrappers Target Condition({defined (USE_CYGWIN_LIBSTDCXX_WRAPPERS)}) -Compile code that relies on Cygwin DLL wrappers to support C++ operator new/delete replacement +Compile code that relies on Cygwin DLL wrappers to support C++ operator new/delete replacement. posix Driver diff --git a/gcc/config/i386/djgpp.opt b/gcc/config/i386/djgpp.opt index 00508021bf1..d52c77dee85 100644 --- a/gcc/config/i386/djgpp.opt +++ b/gcc/config/i386/djgpp.opt @@ -22,7 +22,7 @@ ;; weak symbols, and .gnu.linkonce support. mbnu210 Target Var(TARGET_BNU210) -Ignored (obsolete) +Ignored (obsolete). posix Driver diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 687ae0c1b14..8acf0f4b3a0 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -179,55 +179,55 @@ enum ix86_veclibabi x_ix86_veclibabi_type ;; x86 options m128bit-long-double Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save -sizeof(long double) is 16 +sizeof(long double) is 16. m80387 Target Report Mask(80387) Save -Use hardware fp +Use hardware fp. m96bit-long-double Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save -sizeof(long double) is 12 +sizeof(long double) is 12. mlong-double-80 Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save -Use 80-bit long double +Use 80-bit long double. mlong-double-64 Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save -Use 64-bit long double +Use 64-bit long double. mlong-double-128 Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save -Use 128-bit long double +Use 128-bit long double. maccumulate-outgoing-args Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save -Reserve space for outgoing arguments in the function prologue +Reserve space for outgoing arguments in the function prologue. malign-double Target Report Mask(ALIGN_DOUBLE) Save -Align some doubles on dword boundary +Align some doubles on dword boundary. malign-functions= Target RejectNegative Joined UInteger -Function starts are aligned to this power of 2 +Function starts are aligned to this power of 2. malign-jumps= Target RejectNegative Joined UInteger -Jump targets are aligned to this power of 2 +Jump targets are aligned to this power of 2. malign-loops= Target RejectNegative Joined UInteger -Loop code aligned to this power of 2 +Loop code aligned to this power of 2. malign-stringops Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save -Align destination of the string operations +Align destination of the string operations. malign-data= Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat) -Use the given data alignment +Use the given data alignment. Enum Name(ix86_align_data) Type(enum ix86_align_data) @@ -244,11 +244,11 @@ Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline) march= Target RejectNegative Joined Var(ix86_arch_string) -Generate code for given CPU +Generate code for given CPU. masm= Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT) -Use given assembler dialect +Use given assembler dialect. Enum Name(asm_dialect) Type(enum asm_dialect) @@ -262,15 +262,15 @@ Enum(asm_dialect) String(att) Value(ASM_ATT) mbranch-cost= Target RejectNegative Joined UInteger Var(ix86_branch_cost) -Branches are this expensive (1-5, arbitrary units) +Branches are this expensive (1-5, arbitrary units). mlarge-data-threshold= Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD) -Data greater than given threshold will go into .ldata section in x86-64 medium model +Data greater than given threshold will go into .ldata section in x86-64 medium model. mcmodel= Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32) -Use given x86-64 code model +Use given x86-64 code model. Enum Name(cmodel) Type(enum cmodel) @@ -293,7 +293,7 @@ Enum(cmodel) String(kernel) Value(CM_KERNEL) maddress-mode= Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI) -Use given address mode +Use given address mode. Enum Name(pmode) Type(enum pmode) @@ -310,19 +310,19 @@ Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is depre mfancy-math-387 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save -Generate sin, cos, sqrt for FPU +Generate sin, cos, sqrt for FPU. mforce-drap Target Report Var(ix86_force_drap) -Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack +Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack. mfp-ret-in-387 Target Report Mask(FLOAT_RETURNS) Save -Return values of functions in FPU registers +Return values of functions in FPU registers. mfpmath= Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save -Generate floating point mathematics using given instruction set +Generate floating point mathematics using given instruction set. Enum Name(fpmath_unit) Type(enum fpmath_unit) @@ -351,19 +351,19 @@ Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_38 mhard-float Target RejectNegative Mask(80387) Save -Use hardware fp +Use hardware fp. mieee-fp Target Report Mask(IEEE_FP) Save -Use IEEE math for fp comparisons +Use IEEE math for fp comparisons. minline-all-stringops Target Report Mask(INLINE_ALL_STRINGOPS) Save -Inline all known string operations +Inline all known string operations. minline-stringops-dynamically Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save -Inline memset/memcpy string operations, but perform inline version only for small blocks +Inline memset/memcpy string operations, but perform inline version only for small blocks. mintel-syntax Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) @@ -371,7 +371,7 @@ Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno- mms-bitfields Target Report Mask(MS_BITFIELD_LAYOUT) Save -Use native (MS) bitfield layout +Use native (MS) bitfield layout. mno-align-stringops Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save @@ -387,71 +387,71 @@ Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save momit-leaf-frame-pointer Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save -Omit the frame pointer in leaf functions +Omit the frame pointer in leaf functions. mpc32 Target RejectNegative Report -Set 80387 floating-point precision to 32-bit +Set 80387 floating-point precision to 32-bit. mpc64 Target RejectNegative Report -Set 80387 floating-point precision to 64-bit +Set 80387 floating-point precision to 64-bit. mpc80 Target RejectNegative Report -Set 80387 floating-point precision to 80-bit +Set 80387 floating-point precision to 80-bit. mpreferred-stack-boundary= Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) -Attempt to keep stack aligned to this power of 2 +Attempt to keep stack aligned to this power of 2. mincoming-stack-boundary= Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg) -Assume incoming stack aligned to this power of 2 +Assume incoming stack aligned to this power of 2. mpush-args Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save -Use push instructions to save outgoing arguments +Use push instructions to save outgoing arguments. mred-zone Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save -Use red-zone in the x86-64 code +Use red-zone in the x86-64 code. mregparm= Target RejectNegative Joined UInteger Var(ix86_regparm) -Number of registers used to pass integer arguments +Number of registers used to pass integer arguments. mrtd Target Report Mask(RTD) Save -Alternate calling convention +Alternate calling convention. msoft-float Target InverseMask(80387) Save -Do not use hardware fp +Do not use hardware fp. msseregparm Target RejectNegative Mask(SSEREGPARM) Save -Use SSE register passing conventions for SF and DF mode +Use SSE register passing conventions for SF and DF mode. mstackrealign Target Report Var(ix86_force_align_arg_pointer) Init(-1) -Realign stack in prologue +Realign stack in prologue. mstack-arg-probe Target Report Mask(STACK_PROBE) Save -Enable stack probing +Enable stack probing. mmemcpy-strategy= Target RejectNegative Joined Var(ix86_tune_memcpy_strategy) -Specify memcpy expansion strategy when expected size is known +Specify memcpy expansion strategy when expected size is known. mmemset-strategy= Target RejectNegative Joined Var(ix86_tune_memset_strategy) -Specify memset expansion strategy when expected size is known +Specify memset expansion strategy when expected size is known. mstringop-strategy= Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop) -Chose strategy to generate stringop using +Chose strategy to generate stringop using. Enum Name(stringop_alg) Type(enum stringop_alg) @@ -483,7 +483,7 @@ Enum(stringop_alg) String(vector_loop) Value(vector_loop) mtls-dialect= Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU) -Use given thread-local storage dialect +Use given thread-local storage dialect. Enum Name(tls_dialect) Type(enum tls_dialect) @@ -497,30 +497,30 @@ Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) mtls-direct-seg-refs Target Report Mask(TLS_DIRECT_SEG_REFS) -Use direct references against %gs when accessing tls data +Use direct references against %gs when accessing tls data. mtune= Target RejectNegative Joined Var(ix86_tune_string) -Schedule code for given CPU +Schedule code for given CPU. mtune-ctrl= Target RejectNegative Joined Var(ix86_tune_ctrl_string) -Fine grain control of tune features +Fine grain control of tune features. mno-default Target RejectNegative Var(ix86_tune_no_default) Init(0) -Clear all tune features +Clear all tune features. mdump-tune-features Target RejectNegative Var(ix86_dump_tunes) Init(0) miamcu Target Report Mask(IAMCU) -Generate code that conforms to Intel MCU psABI +Generate code that conforms to Intel MCU psABI. mabi= Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI) -Generate code that conforms to the given ABI +Generate code that conforms to the given ABI. Enum Name(calling_abi) Type(enum calling_abi) @@ -534,7 +534,7 @@ Enum(calling_abi) String(ms) Value(MS_ABI) mveclibabi= Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none) -Vector library ABI to use +Vector library ABI to use. Enum Name(ix86_veclibabi) Type(enum ix86_veclibabi) @@ -548,7 +548,7 @@ Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) mvect8-ret-in-mem Target Report Mask(VECT8_RETURNS) Save -Return 8-byte vectors in memory +Return 8-byte vectors in memory. mrecip Target Report Mask(RECIP) Save @@ -585,63 +585,63 @@ Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vec m32 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save -Generate 32bit i386 code +Generate 32bit i386 code. m64 Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save -Generate 64bit x86-64 code +Generate 64bit x86-64 code. mx32 Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save -Generate 32bit x86-64 code +Generate 32bit x86-64 code. m16 Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save -Generate 16bit i386 code +Generate 16bit i386 code. mmmx Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save -Support MMX built-in functions +Support MMX built-in functions. m3dnow Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save -Support 3DNow! built-in functions +Support 3DNow! built-in functions. m3dnowa Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save -Support Athlon 3Dnow! built-in functions +Support Athlon 3Dnow! built-in functions. msse Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save -Support MMX and SSE built-in functions and code generation +Support MMX and SSE built-in functions and code generation. msse2 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save -Support MMX, SSE and SSE2 built-in functions and code generation +Support MMX, SSE and SSE2 built-in functions and code generation. msse3 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation +Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation. mssse3 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation +Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation. msse4.1 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation. msse4.2 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. msse4 Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. mno-sse4 Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save -Do not support SSE4.1 and SSE4.2 built-in functions and code generation +Do not support SSE4.1 and SSE4.2 built-in functions and code generation. msse5 Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) @@ -649,55 +649,55 @@ Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) mavx Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation. mavx2 Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation. mavx512f Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation. mavx512pf Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation. mavx512er Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation. mavx512cd Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation. mavx512dq Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation. mavx512bw Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation. mavx512vl Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation. mavx512ifma Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation. mavx512vbmi Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation. mfma Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation. msse4a Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save -Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation +Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation. mfma4 Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save @@ -721,71 +721,71 @@ Support code generation of popcnt instruction. mbmi Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save -Support BMI built-in functions and code generation +Support BMI built-in functions and code generation. mbmi2 Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save -Support BMI2 built-in functions and code generation +Support BMI2 built-in functions and code generation. mlzcnt Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save -Support LZCNT built-in function and code generation +Support LZCNT built-in function and code generation. mhle Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save -Support Hardware Lock Elision prefixes +Support Hardware Lock Elision prefixes. mrdseed Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save -Support RDSEED instruction +Support RDSEED instruction. mprfchw Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save -Support PREFETCHW instruction +Support PREFETCHW instruction. madx Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save -Support flag-preserving add-carry instructions +Support flag-preserving add-carry instructions. mclflushopt Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save -Support CLFLUSHOPT instructions +Support CLFLUSHOPT instructions. mclzero Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags) Save -Support CLZERO instructions +Support CLZERO instructions. mclwb Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save -Support CLWB instruction +Support CLWB instruction. mpcommit Target Report Mask(ISA_PCOMMIT) Var(ix86_isa_flags) Save -Support PCOMMIT instruction +Support PCOMMIT instruction. mfxsr Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save -Support FXSAVE and FXRSTOR instructions +Support FXSAVE and FXRSTOR instructions. mxsave Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save -Support XSAVE and XRSTOR instructions +Support XSAVE and XRSTOR instructions. mxsaveopt Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save -Support XSAVEOPT instruction +Support XSAVEOPT instruction. mxsavec Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save -Support XSAVEC instructions +Support XSAVEC instructions. mxsaves Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save -Support XSAVES and XRSTORS instructions +Support XSAVES and XRSTORS instructions. mtbm Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save -Support TBM built-in functions and code generation +Support TBM built-in functions and code generation. mcx16 Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save @@ -805,35 +805,35 @@ Support code generation of crc32 instruction. maes Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save -Support AES built-in functions and code generation +Support AES built-in functions and code generation. msha Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save -Support SHA1 and SHA256 built-in functions and code generation +Support SHA1 and SHA256 built-in functions and code generation. mpclmul Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save -Support PCLMUL built-in functions and code generation +Support PCLMUL built-in functions and code generation. msse2avx Target Report Var(ix86_sse2avx) -Encode SSE instructions with VEX prefix +Encode SSE instructions with VEX prefix. mfsgsbase Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save -Support FSGSBASE built-in functions and code generation +Support FSGSBASE built-in functions and code generation. mrdrnd Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save -Support RDRND built-in functions and code generation +Support RDRND built-in functions and code generation. mf16c Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save -Support F16C built-in functions and code generation +Support F16C built-in functions and code generation. mprefetchwt1 Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save -Support PREFETCHWT1 built-in functions and code generation +Support PREFETCHWT1 built-in functions and code generation. mfentry Target Report Var(flag_fentry) Init(-1) @@ -854,31 +854,31 @@ Skip setting up RAX register when passing variable arguments. m8bit-idiv Target Report Mask(USE_8BIT_IDIV) Save -Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check +Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check. mavx256-split-unaligned-load Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save -Split 32-byte AVX unaligned load +Split 32-byte AVX unaligned load. mavx256-split-unaligned-store Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save -Split 32-byte AVX unaligned store +Split 32-byte AVX unaligned store. mrtm Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save -Support RTM built-in functions and code generation +Support RTM built-in functions and code generation. mmpx Target Report Mask(ISA_MPX) Var(ix86_isa_flags) Save -Support MPX code generation +Support MPX code generation. mmwaitx Target Report Mask(ISA_MWAITX) Var(ix86_isa_flags) Save -Support MWAITX and MONITORX built-in functions and code generation +Support MWAITX and MONITORX built-in functions and code generation. mstack-protector-guard= Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS) -Use given stack-protector guard +Use given stack-protector guard. Enum Name(stack_protector_guard) Type(enum stack_protector_guard) diff --git a/gcc/config/i386/interix.opt b/gcc/config/i386/interix.opt index db7fb73dd63..04de55b1c2e 100644 --- a/gcc/config/i386/interix.opt +++ b/gcc/config/i386/interix.opt @@ -29,6 +29,6 @@ Driver mpe-aligned-commons Target Var(use_pe_aligned_common) Init(HAVE_GAS_ALIGNED_COMM) -Use the GNU extension to the PE format for aligned common data +Use the GNU extension to the PE format for aligned common data. ; This comment is to ensure we retain the blank line above. diff --git a/gcc/config/i386/mingw-w64.opt b/gcc/config/i386/mingw-w64.opt index ca7b686ccb8..40f06c3e30c 100644 --- a/gcc/config/i386/mingw-w64.opt +++ b/gcc/config/i386/mingw-w64.opt @@ -20,6 +20,6 @@ municode Target -Use unicode startup and define UNICODE macro +Use unicode startup and define UNICODE macro. ; Retain blank line above. diff --git a/gcc/config/i386/mingw.opt b/gcc/config/i386/mingw.opt index 322b66cb204..03c7a14703f 100644 --- a/gcc/config/i386/mingw.opt +++ b/gcc/config/i386/mingw.opt @@ -26,7 +26,7 @@ Driver Wpedantic-ms-format C ObjC C++ ObjC++ Var(warn_pedantic_ms_format) Init(1) Warning -Warn about none ISO msvcrt scanf/printf width extensions +Warn about none ISO msvcrt scanf/printf width extensions. fset-stack-executable Common Report Var(flag_setstackexecutable) Init(1) Optimization diff --git a/gcc/config/ia64/ia64.opt b/gcc/config/ia64/ia64.opt index a5bea229d8a..4e0af4238ef 100644 --- a/gcc/config/ia64/ia64.opt +++ b/gcc/config/ia64/ia64.opt @@ -25,101 +25,101 @@ enum processor_type ia64_tune = PROCESSOR_ITANIUM2 mbig-endian Target Report RejectNegative Mask(BIG_ENDIAN) -Generate big endian code +Generate big endian code. mlittle-endian Target Report RejectNegative InverseMask(BIG_ENDIAN) -Generate little endian code +Generate little endian code. mgnu-as Target Report Mask(GNU_AS) -Generate code for GNU as +Generate code for GNU as. mgnu-ld Target Report Mask(GNU_LD) -Generate code for GNU ld +Generate code for GNU ld. mvolatile-asm-stop Target Report Mask(VOL_ASM_STOP) -Emit stop bits before and after volatile extended asms +Emit stop bits before and after volatile extended asms. mregister-names Target Mask(REG_NAMES) -Use in/loc/out register names +Use in/loc/out register names. mno-sdata Target Report RejectNegative Mask(NO_SDATA) msdata Target Report RejectNegative InverseMask(NO_SDATA) -Enable use of sdata/scommon/sbss +Enable use of sdata/scommon/sbss. mno-pic Target Report RejectNegative Mask(NO_PIC) -Generate code without GP reg +Generate code without GP reg. mconstant-gp Target Report RejectNegative Mask(CONST_GP) -gp is constant (but save/restore gp on indirect calls) +gp is constant (but save/restore gp on indirect calls). mauto-pic Target Report RejectNegative Mask(AUTO_PIC) -Generate self-relocatable code +Generate self-relocatable code. minline-float-divide-min-latency Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1) -Generate inline floating point division, optimize for latency +Generate inline floating point division, optimize for latency. minline-float-divide-max-throughput Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2) -Generate inline floating point division, optimize for throughput +Generate inline floating point division, optimize for throughput. mno-inline-float-divide Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0) minline-int-divide-min-latency Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1) -Generate inline integer division, optimize for latency +Generate inline integer division, optimize for latency. minline-int-divide-max-throughput Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2) -Generate inline integer division, optimize for throughput +Generate inline integer division, optimize for throughput. mno-inline-int-divide Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0) -Do not inline integer division +Do not inline integer division. minline-sqrt-min-latency Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1) -Generate inline square root, optimize for latency +Generate inline square root, optimize for latency. minline-sqrt-max-throughput Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2) -Generate inline square root, optimize for throughput +Generate inline square root, optimize for throughput. mno-inline-sqrt Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0) -Do not inline square root +Do not inline square root. mdwarf2-asm Target Report Mask(DWARF2_ASM) -Enable Dwarf 2 line debug info via GNU as +Enable Dwarf 2 line debug info via GNU as. mearly-stop-bits Target Report Mask(EARLY_STOP_BITS) -Enable earlier placing stop bits for better scheduling +Enable earlier placing stop bits for better scheduling. mfixed-range= Target RejectNegative Joined Var(ia64_deferred_options) Defer -Specify range of registers to make fixed +Specify range of registers to make fixed. mtls-size= Target RejectNegative Joined UInteger Var(ia64_tls_size) Init(22) -Specify bit size of immediate TLS offsets +Specify bit size of immediate TLS offsets. mtune= Target RejectNegative Joined Enum(ia64_tune) Var(ia64_tune) -Schedule code for given CPU +Schedule code for given CPU. Enum Name(ia64_tune) Type(enum processor_type) @@ -133,35 +133,35 @@ Enum(ia64_tune) String(mckinley) Value(PROCESSOR_ITANIUM2) msched-br-data-spec Target Report Var(mflag_sched_br_data_spec) Init(0) -Use data speculation before reload +Use data speculation before reload. msched-ar-data-spec Target Report Var(mflag_sched_ar_data_spec) Init(1) -Use data speculation after reload +Use data speculation after reload. msched-control-spec Target Report Var(mflag_sched_control_spec) Init(2) -Use control speculation +Use control speculation. msched-br-in-data-spec Target Report Var(mflag_sched_br_in_data_spec) Init(1) -Use in block data speculation before reload +Use in block data speculation before reload. msched-ar-in-data-spec Target Report Var(mflag_sched_ar_in_data_spec) Init(1) -Use in block data speculation after reload +Use in block data speculation after reload. msched-in-control-spec Target Report Var(mflag_sched_in_control_spec) Init(1) -Use in block control speculation +Use in block control speculation. msched-spec-ldc Target Report Var(mflag_sched_spec_ldc) Init(1) -Use simple data speculation check +Use simple data speculation check. msched-spec-control-ldc Target Report Var(mflag_sched_spec_control_ldc) Init(0) -Use simple data speculation check for control speculation +Use simple data speculation check for control speculation. msched-prefer-non-data-spec-insns Target Ignore Warn(switch %qs is no longer supported) @@ -171,26 +171,26 @@ Target Ignore Warn(switch %qs is no longer supported) msched-count-spec-in-critical-path Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0) -Count speculative dependencies while calculating priority of instructions +Count speculative dependencies while calculating priority of instructions. msched-stop-bits-after-every-cycle Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1) -Place a stop bit after every cycle when scheduling +Place a stop bit after every cycle when scheduling. msched-fp-mem-deps-zero-cost Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0) -Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group +Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group. msched-max-memory-insns= Target RejectNegative Joined UInteger Var(ia64_max_memory_insns) Init(1) -Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1 +Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1. msched-max-memory-insns-hard-limit Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0) -Disallow more than 'msched-max-memory-insns' in instruction group. Otherwise, limit is 'soft' (prefer non-memory operations when limit is reached) +Disallow more than 'msched-max-memory-insns' in instruction group. Otherwise, limit is 'soft' (prefer non-memory operations when limit is reached). msel-sched-dont-check-control-spec Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0) -Don't generate checks for control speculation in selective scheduling +Don't generate checks for control speculation in selective scheduling. ; This comment is to ensure we retain the blank line above. diff --git a/gcc/config/ia64/ilp32.opt b/gcc/config/ia64/ilp32.opt index bcb64737eb9..2083a25219e 100644 --- a/gcc/config/ia64/ilp32.opt +++ b/gcc/config/ia64/ilp32.opt @@ -1,7 +1,7 @@ milp32 Target Report RejectNegative Mask(ILP32) -Generate ILP32 code +Generate ILP32 code. mlp64 Target Report RejectNegative InverseMask(ILP32) -Generate LP64 code +Generate LP64 code. diff --git a/gcc/config/iq2000/iq2000.opt b/gcc/config/iq2000/iq2000.opt index 2083b0c5ea0..721b0804be3 100644 --- a/gcc/config/iq2000/iq2000.opt +++ b/gcc/config/iq2000/iq2000.opt @@ -28,7 +28,7 @@ enum processor_type iq2000_tune = PROCESSOR_DEFAULT ; This option has no effect at the moment. march= Target RejectNegative Joined Enum(iq2000_arch) -Specify CPU for code generation purposes +Specify CPU for code generation purposes. Enum Name(iq2000_arch) Type(int) @@ -44,7 +44,7 @@ Enum(iq2000_arch) String(iq2000) Value(0) mcpu= Target RejectNegative Joined Enum(iq2000_tune) Var(iq2000_tune) -Specify CPU for scheduling purposes +Specify CPU for scheduling purposes. Enum Name(iq2000_tune) Type(enum processor_type) @@ -58,17 +58,17 @@ Enum(iq2000_tune) String(iq2000) Value(PROCESSOR_IQ2000) membedded-data Target Mask(EMBEDDED_DATA) -Use ROM instead of RAM +Use ROM instead of RAM. mgpopt Target Mask(GPOPT) -Use GP relative sdata/sbss sections +Use GP relative sdata/sbss sections. ; Not used by the compiler proper. mno-crt0 Target RejectNegative -No default crt0.o +No default crt0.o. muninit-const-in-rodata Target Mask(UNINIT_CONST_IN_RODATA) -Put uninitialized constants in ROM (needs -membedded-data) +Put uninitialized constants in ROM (needs -membedded-data). diff --git a/gcc/config/linux.opt b/gcc/config/linux.opt index ef055a7d095..3f6115f46a0 100644 --- a/gcc/config/linux.opt +++ b/gcc/config/linux.opt @@ -21,16 +21,16 @@ mbionic Target Report RejectNegative Var(linux_libc,LIBC_BIONIC) Init(DEFAULT_LIBC) Negative(mglibc) -Use Bionic C library +Use Bionic C library. mglibc Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc) -Use GNU C library +Use GNU C library. muclibc Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mmusl) -Use uClibc C library +Use uClibc C library. mmusl Target Report RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mbionic) -Use musl C library +Use musl C library. diff --git a/gcc/config/lm32/lm32.opt b/gcc/config/lm32/lm32.opt index 9e6c10b0d5d..4090b3db365 100644 --- a/gcc/config/lm32/lm32.opt +++ b/gcc/config/lm32/lm32.opt @@ -21,20 +21,20 @@ mmultiply-enabled Target Report Mask(MULTIPLY_ENABLED) -Enable multiply instructions +Enable multiply instructions. mdivide-enabled Target Report Mask(DIVIDE_ENABLED) -Enable divide and modulus instructions +Enable divide and modulus instructions. mbarrel-shift-enabled Target Report Mask(BARREL_SHIFT_ENABLED) -Enable barrel shift instructions +Enable barrel shift instructions. msign-extend-enabled Target Report Mask(SIGN_EXTEND_ENABLED) -Enable sign extend instructions +Enable sign extend instructions. muser-enabled Target Report Mask(USER_ENABLED) -Enable user-defined instructions +Enable user-defined instructions. diff --git a/gcc/config/lynx.opt b/gcc/config/lynx.opt index 80a1bbd0763..39bf9ee26b1 100644 --- a/gcc/config/lynx.opt +++ b/gcc/config/lynx.opt @@ -20,12 +20,12 @@ mlegacy-threads Target RejectNegative -Support legacy multi-threading +Support legacy multi-threading. mshared Target RejectNegative -Use shared libraries +Use shared libraries. mthreads Target RejectNegative -Support multi-threading +Support multi-threading. diff --git a/gcc/config/m32c/m32c.opt b/gcc/config/m32c/m32c.opt index 14ea13bb8f3..0ff13fa5ee1 100644 --- a/gcc/config/m32c/m32c.opt +++ b/gcc/config/m32c/m32c.opt @@ -20,24 +20,24 @@ msim Target --msim Use simulator runtime +-msim Use simulator runtime. mcpu=r8c Target RejectNegative Var(target_cpu,'r') Init('r') --mcpu=r8c Compile code for R8C variants +-mcpu=r8c Compile code for R8C variants. mcpu=m16c Target RejectNegative Var(target_cpu,'6') --mcpu=m16c Compile code for M16C variants +-mcpu=m16c Compile code for M16C variants. mcpu=m32cm Target RejectNegative Var(target_cpu,'m') --mcpu=m32cm Compile code for M32CM variants +-mcpu=m32cm Compile code for M32CM variants. mcpu=m32c Target RejectNegative Var(target_cpu,'3') --mcpu=m32c Compile code for M32C variants +-mcpu=m32c Compile code for M32C variants. memregs= Target RejectNegative Joined UInteger Var(target_memregs) Init(16) --memregs= Number of memreg bytes (default: 16, range: 0..16) +-memregs= Number of memreg bytes (default: 16, range: 0..16). diff --git a/gcc/config/m32r/m32r.opt b/gcc/config/m32r/m32r.opt index 85a197b63e2..c87b6875621 100644 --- a/gcc/config/m32r/m32r.opt +++ b/gcc/config/m32r/m32r.opt @@ -31,51 +31,51 @@ enum m32r_sdata m32r_sdata_selected = M32R_SDATA_DEFAULT m32rx Target Report RejectNegative Mask(M32RX) -Compile for the m32rx +Compile for the m32rx. m32r2 Target Report RejectNegative Mask(M32R2) -Compile for the m32r2 +Compile for the m32r2. m32r Target RejectNegative -Compile for the m32r +Compile for the m32r. malign-loops Target Report Mask(ALIGN_LOOPS) -Align all loops to 32 byte boundary +Align all loops to 32 byte boundary. mbranch-cost=1 Target Report RejectNegative Mask(BRANCH_COST) -Prefer branches over conditional execution +Prefer branches over conditional execution. mbranch-cost=2 Target Report RejectNegative InverseMask(BRANCH_COST) -Give branches their default cost +Give branches their default cost. mdebug Target Mask(DEBUG) -Display compile time statistics +Display compile time statistics. mflush-func= Target RejectNegative Joined Var(m32r_cache_flush_func) Init(CACHE_FLUSH_FUNC) -Specify cache flush function +Specify cache flush function. mflush-trap= Target RejectNegative Joined UInteger Var(m32r_cache_flush_trap) Init(CACHE_FLUSH_TRAP) -Specify cache flush trap number +Specify cache flush trap number. missue-rate=1 Target Report RejectNegative Mask(LOW_ISSUE_RATE) -Only issue one instruction per cycle +Only issue one instruction per cycle. missue-rate=2 Target Report RejectNegative InverseMask(LOW_ISSUE_RATE) -Allow two instructions to be issued per cycle +Allow two instructions to be issued per cycle. mmodel= Target RejectNegative Joined Enum(m32r_model) Var(m32r_model_selected) -Code size: small, medium or large +Code size: small, medium or large. Enum Name(m32r_model) Type(enum m32r_model) @@ -91,18 +91,18 @@ Enum(m32r_model) String(large) Value(M32R_MODEL_LARGE) mno-flush-func Target RejectNegative -Don't call any cache flush functions +Don't call any cache flush functions. mno-flush-trap Target RejectNegative Var(m32r_cache_flush_trap, -1) -Don't call any cache flush trap +Don't call any cache flush trap. ; mrelax ; Target Mask(RELAX) msdata= Target RejectNegative Joined Enum(m32r_sdata) Var(m32r_sdata_selected) -Small data area: none, sdata, use +Small data area: none, sdata, use. Enum Name(m32r_sdata) Type(enum m32r_sdata) diff --git a/gcc/config/m68k/ieee.opt b/gcc/config/m68k/ieee.opt index 6605f2171cf..24144072734 100644 --- a/gcc/config/m68k/ieee.opt +++ b/gcc/config/m68k/ieee.opt @@ -21,4 +21,4 @@ ; This option is ignored by gcc mieee-fp Target RejectNegative -Use IEEE math for fp comparisons +Use IEEE math for fp comparisons. diff --git a/gcc/config/m68k/m68k.opt b/gcc/config/m68k/m68k.opt index 67d298b4058..46010e50046 100644 --- a/gcc/config/m68k/m68k.opt +++ b/gcc/config/m68k/m68k.opt @@ -27,169 +27,169 @@ const char *m68k_library_id_string = "_current_shared_library_a5_offset_" m5200 Target RejectNegative Alias(mcpu=, 5206) -Generate code for a 520X +Generate code for a 520X. m5206e Target RejectNegative Alias(mcpu=, 5206e) -Generate code for a 5206e +Generate code for a 5206e. m528x Target RejectNegative Alias(mcpu=, 528x) -Generate code for a 528x +Generate code for a 528x. m5307 Target RejectNegative Alias(mcpu=, 5307) -Generate code for a 5307 +Generate code for a 5307. m5407 Target RejectNegative Alias(mcpu=, 5407) -Generate code for a 5407 +Generate code for a 5407. m68000 Target RejectNegative Alias(mcpu=, 68000) -Generate code for a 68000 +Generate code for a 68000. m68010 Target RejectNegative Alias(mcpu=, 68010) -Generate code for a 68010 +Generate code for a 68010. m68020 Target RejectNegative Alias(mcpu=, 68020) -Generate code for a 68020 +Generate code for a 68020. m68020-40 Target RejectNegative -Generate code for a 68040, without any new instructions +Generate code for a 68040, without any new instructions. m68020-60 Target RejectNegative -Generate code for a 68060, without any new instructions +Generate code for a 68060, without any new instructions. m68030 Target RejectNegative Alias(mcpu=, 68030) -Generate code for a 68030 +Generate code for a 68030. m68040 Target RejectNegative Alias(mcpu=, 68040) -Generate code for a 68040 +Generate code for a 68040. m68060 Target RejectNegative Alias(mcpu=, 68060) -Generate code for a 68060 +Generate code for a 68060. m68302 Target RejectNegative Alias(mcpu=, 68302) -Generate code for a 68302 +Generate code for a 68302. m68332 Target RejectNegative Alias(mcpu=, 68332) -Generate code for a 68332 +Generate code for a 68332. ; Has no effect on gcc m68851 Target -Generate code for a 68851 +Generate code for a 68851. m68881 Target RejectNegative Mask(HARD_FLOAT) -Generate code that uses 68881 floating-point instructions +Generate code that uses 68881 floating-point instructions. malign-int Target Report Mask(ALIGN_INT) -Align variables on a 32-bit boundary +Align variables on a 32-bit boundary. march= Target RejectNegative Joined Enum(m68k_isa) Var(m68k_arch_option) -Specify the name of the target architecture +Specify the name of the target architecture. mbitfield Target Report Mask(BITFIELD) -Use the bit-field instructions +Use the bit-field instructions. mc68000 Target RejectNegative Alias(mcpu=, 68000) -Generate code for a 68000 +Generate code for a 68000. mc68020 Target RejectNegative Alias(mcpu=, 68020) -Generate code for a 68020 +Generate code for a 68020. mcfv4e Target RejectNegative Alias(mcpu=, 547x) -Generate code for a ColdFire v4e +Generate code for a ColdFire v4e. mcpu= Target RejectNegative Joined Enum(target_device) Var(m68k_cpu_option) Init(unk_device) -Specify the target CPU +Specify the target CPU. mcpu32 Target RejectNegative Alias(mcpu=, 68332) -Generate code for a cpu32 +Generate code for a cpu32. mdiv Target Report Mask(CF_HWDIV) -Use hardware division instructions on ColdFire +Use hardware division instructions on ColdFire. mfidoa Target RejectNegative -Generate code for a Fido A +Generate code for a Fido A. mhard-float Target RejectNegative Mask(HARD_FLOAT) -Generate code which uses hardware floating point instructions +Generate code which uses hardware floating point instructions. mid-shared-library Target Report Mask(ID_SHARED_LIBRARY) -Enable ID based shared library +Enable ID based shared library. mnobitfield Target RejectNegative InverseMask(BITFIELD) -Do not use the bit-field instructions +Do not use the bit-field instructions. mnortd Target RejectNegative InverseMask(RTD) -Use normal calling convention +Use normal calling convention. mnoshort Target RejectNegative InverseMask(SHORT) -Consider type 'int' to be 32 bits wide +Consider type 'int' to be 32 bits wide. mpcrel Target Report Mask(PCREL) -Generate pc-relative code +Generate pc-relative code. mrtd Target Report Mask(RTD) -Use different calling convention using 'rtd' +Use different calling convention using 'rtd'. msep-data Target Report Mask(SEP_DATA) -Enable separate data segment +Enable separate data segment. mshared-library-id= Target RejectNegative Joined UInteger -ID of shared library to build +ID of shared library to build. mshort Target Report Mask(SHORT) -Consider type 'int' to be 16 bits wide +Consider type 'int' to be 16 bits wide. msoft-float Target RejectNegative InverseMask(HARD_FLOAT) -Generate code with library calls for floating point +Generate code with library calls for floating point. mstrict-align Target Report Mask(STRICT_ALIGNMENT) -Do not use unaligned memory references +Do not use unaligned memory references. mtune= Target RejectNegative Joined Enum(uarch_type) Var(m68k_tune_option) Init(unk_arch) -Tune for the specified target CPU or architecture +Tune for the specified target CPU or architecture. mxgot Target Report Mask(XGOT) -Support more than 8192 GOT entries on ColdFire +Support more than 8192 GOT entries on ColdFire. mxtls Target Report Mask(XTLS) -Support TLS segment larger than 64K +Support TLS segment larger than 64K. diff --git a/gcc/config/mcore/mcore.opt b/gcc/config/mcore/mcore.opt index 342fd54d909..396f689be3d 100644 --- a/gcc/config/mcore/mcore.opt +++ b/gcc/config/mcore/mcore.opt @@ -28,48 +28,48 @@ Generate code for the M*Core M340 m4byte-functions Target Report Mask(OVERALIGN_FUNC) -Force functions to be aligned to a 4 byte boundary +Force functions to be aligned to a 4 byte boundary. mbig-endian Target RejectNegative Report InverseMask(LITTLE_END) -Generate big-endian code +Generate big-endian code. mcallgraph-data Target Report Mask(CG_DATA) -Emit call graph information +Emit call graph information. mdiv Target Report Mask(DIV) -Use the divide instruction +Use the divide instruction. mhardlit Target Report Mask(HARDLIT) -Inline constants if it can be done in 2 insns or less +Inline constants if it can be done in 2 insns or less. mlittle-endian Target RejectNegative Report Mask(LITTLE_END) -Generate little-endian code +Generate little-endian code. ; Not used by the compiler proper. mno-lsim Target RejectNegative -Assume that run-time support has been provided, so omit -lsim from the linker command line +Assume that run-time support has been provided, so omit -lsim from the linker command line. mrelax-immediates Target Report Mask(RELAX_IMM) -Use arbitrary sized immediates in bit operations +Use arbitrary sized immediates in bit operations. mslow-bytes Target Report Mask(SLOW_BYTES) -Prefer word accesses over byte accesses +Prefer word accesses over byte accesses. ; Maximum size we are allowed to grow the stack in a single operation. ; If we want more, we must do it in increments of at most this size. ; If this value is 0, we don't check at all. mstack-increment= Target RejectNegative Joined UInteger Var(mcore_stack_increment) Init(STACK_UNITS_MAXSTEP) -Set the maximum amount for a single stack increment operation +Set the maximum amount for a single stack increment operation. mwide-bitfields Target Report Mask(W_FIELD) -Always treat bitfields as int-sized +Always treat bitfields as int-sized. diff --git a/gcc/config/mep/mep.opt b/gcc/config/mep/mep.opt index fc8704dc12c..64864419e92 100644 --- a/gcc/config/mep/mep.opt +++ b/gcc/config/mep/mep.opt @@ -20,139 +20,139 @@ Mask(IVC2) mabsdiff Target Mask(OPT_ABSDIFF) -Enable absolute difference instructions +Enable absolute difference instructions. mall-opts Target RejectNegative -Enable all optional instructions +Enable all optional instructions. maverage Target Mask(OPT_AVERAGE) -Enable average instructions +Enable average instructions. mbased= Target Joined Var(mep_based_cutoff) RejectNegative UInteger Init(0) -Variables this size and smaller go in the based section. (default 0) +Variables this size and smaller go in the based section. (default 0). mbitops Target Mask(OPT_BITOPS) -Enable bit manipulation instructions +Enable bit manipulation instructions. mc= Target Joined Var(mep_const_section) RejectNegative -Section to put all const variables in (tiny, near, far) (no default) +Section to put all const variables in (tiny, near, far) (no default). mclip Target Mask(OPT_CLIP) -Enable clip instructions +Enable clip instructions. mconfig= Target Joined Var(mep_config_string) RejectNegative -Configuration name +Configuration name. mcop Target Mask(COP) -Enable MeP Coprocessor +Enable MeP Coprocessor. mcop32 Target Mask(COP) RejectNegative -Enable MeP Coprocessor with 32-bit registers +Enable MeP Coprocessor with 32-bit registers. mcop64 Target Mask(64BIT_CR_REGS) RejectNegative -Enable MeP Coprocessor with 64-bit registers +Enable MeP Coprocessor with 64-bit registers. mivc2 Target RejectNegative Var(mep_deferred_options) Defer -Enable IVC2 scheduling +Enable IVC2 scheduling. mdc Target Mask(DC) RejectNegative -Const variables default to the near section +Const variables default to the near section. mdebug Target Disabled Undocumented mdiv Target Mask(OPT_DIV) -Enable 32-bit divide instructions +Enable 32-bit divide instructions. meb Target InverseMask(LITTLE_ENDIAN) RejectNegative -Use big-endian byte order +Use big-endian byte order. mel Target Mask(LITTLE_ENDIAN) RejectNegative -Use little-endian byte order +Use little-endian byte order. mfar Driver RejectNegative mio-volatile Target Mask(IO_VOLATILE) -__io vars are volatile by default +__io vars are volatile by default. ml Target Mask(L) RejectNegative -All variables default to the far section +All variables default to the far section. mleadz Target Mask(OPT_LEADZ) -Enable leading zero instructions +Enable leading zero instructions. mlibrary Target Mask(LIBRARY) RejectNegative Undocumented mm Target Mask(M) RejectNegative -All variables default to the near section +All variables default to the near section. mminmax Target Mask(OPT_MINMAX) -Enable min/max instructions +Enable min/max instructions. mmult Target Mask(OPT_MULT) -Enable 32-bit multiply instructions +Enable 32-bit multiply instructions. mno-opts Target RejectNegative -Disable all optional instructions +Disable all optional instructions. mrand-tpgp Target Mask(RAND_TPGP) RejectNegative Undocumented mrepeat Target Mask(OPT_REPEAT) -Allow gcc to use the repeat/erepeat instructions +Allow gcc to use the repeat/erepeat instructions. ms Target Mask(S) RejectNegative -All variables default to the tiny section +All variables default to the tiny section. msatur Target Mask(OPT_SATUR) -Enable saturation instructions +Enable saturation instructions. msdram Target -Use sdram version of runtime +Use sdram version of runtime. msim Target RejectNegative -Use simulator runtime +Use simulator runtime. msimnovec Target RejectNegative -Use simulator runtime without vectors +Use simulator runtime without vectors. mtf Target Mask(TF) RejectNegative -All functions default to the far section +All functions default to the far section. mtiny= Target Joined Var(mep_tiny_cutoff) RejectNegative UInteger Init(4) -Variables this size and smaller go in the tiny section. (default 4) +Variables this size and smaller go in the tiny section. (default 4). mvl32 Target InverseMask(OPT_VL64) Undocumented RejectNegative diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt index a1447a5b27b..360a8d57e5b 100644 --- a/gcc/config/microblaze/microblaze.opt +++ b/gcc/config/microblaze/microblaze.opt @@ -37,91 +37,91 @@ Driver msoft-float Target Report RejectNegative Mask(SOFT_FLOAT) -Use software emulation for floating point (default) +Use software emulation for floating point (default). mhard-float Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) -Use hardware floating point instructions +Use hardware floating point instructions. msmall-divides Target Mask(SMALL_DIVIDES) -Use table lookup optimization for small signed integer divisions +Use table lookup optimization for small signed integer divisions. mcpu= Target RejectNegative Joined Var(microblaze_select_cpu) --mcpu=PROCESSOR Use features of and schedule code for given CPU +-mcpu=PROCESSOR Use features of and schedule code for given CPU. mmemcpy Target Mask(MEMCPY) -Don't optimize block moves, use memcpy +Don't optimize block moves, use memcpy. mbig-endian Target Report RejectNegative InverseMask(LITTLE_ENDIAN) -Assume target CPU is configured as big endian +Assume target CPU is configured as big endian. mlittle-endian Target Report RejectNegative Mask(LITTLE_ENDIAN) -Assume target CPU is configured as little endian +Assume target CPU is configured as little endian. mxl-soft-mul Target Mask(SOFT_MUL) -Use the soft multiply emulation (default) +Use the soft multiply emulation (default). mxl-reorder Target Var(TARGET_REORDER) Init(2) -Use reorder instructions (swap and byte reversed load/store) (default) +Use reorder instructions (swap and byte reversed load/store) (default). mxl-soft-div Target Mask(SOFT_DIV) -Use the software emulation for divides (default) +Use the software emulation for divides (default). mxl-barrel-shift Target Mask(BARREL_SHIFT) -Use the hardware barrel shifter instead of emulation +Use the hardware barrel shifter instead of emulation. mxl-pattern-compare Target Mask(PATTERN_COMPARE) -Use pattern compare instructions +Use pattern compare instructions. mxl-stack-check Target Mask(STACK_CHECK) Warn(%qs is deprecated; use -fstack-check) -Check for stack overflow at runtime +Check for stack overflow at runtime. mxl-gp-opt Target Mask(XLGPOPT) -Use GP relative sdata/sbss sections +Use GP relative sdata/sbss sections. mno-clearbss Target RejectNegative Var(flag_zero_initialized_in_bss, 0) Warn(%qs is deprecated; use -fno-zero-initialized-in-bss) -Clear the BSS to zero and place zero initialized in BSS +Clear the BSS to zero and place zero initialized in BSS. mxl-multiply-high Target Mask(MULTIPLY_HIGH) -Use multiply high instructions for high part of 32x32 multiply +Use multiply high instructions for high part of 32x32 multiply. mxl-float-convert Target Mask(FLOAT_CONVERT) -Use hardware floating point conversion instructions +Use hardware floating point conversion instructions. mxl-float-sqrt Target Mask(FLOAT_SQRT) -Use hardware floating point square root instruction +Use hardware floating point square root instruction. mxl-mode-executable Target Mask(XL_MODE_EXECUTABLE) -Description for mxl-mode-executable +Description for mxl-mode-executable. mxl-mode-xmdstub Target Mask(XL_MODE_XMDSTUB) -Description for mxl-mode-xmdstub +Description for mxl-mode-xmdstub. mxl-mode-bootstrap Target Mask(XL_MODE_BOOTSTRAP) -Description for mxl-mode-bootstrap +Description for mxl-mode-bootstrap. mxl-mode-novectors Target Mask(XL_MODE_NOVECTORS) -Description for mxl-mode-novectors +Description for mxl-mode-novectors. mxl-mode-xilkernel Target diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index b979eb51c59..53fca28b660 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -29,7 +29,7 @@ Driver mabi= Target RejectNegative Joined Enum(mips_abi) Var(mips_abi) Init(MIPS_ABI_DEFAULT) --mabi=ABI Generate code that conforms to the given ABI +-mabi=ABI Generate code that conforms to the given ABI. Enum Name(mips_abi) Type(int) @@ -52,39 +52,39 @@ Enum(mips_abi) String(eabi) Value(ABI_EABI) mabicalls Target Report Mask(ABICALLS) -Generate code that can be used in SVR4-style dynamic objects +Generate code that can be used in SVR4-style dynamic objects. mmad Target Report Var(TARGET_MAD) -Use PMC-style 'mad' instructions +Use PMC-style 'mad' instructions. mimadd Target Report Mask(IMADD) -Use integer madd/msub instructions +Use integer madd/msub instructions. march= Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value) --march=ISA Generate code for the given ISA +-march=ISA Generate code for the given ISA. mbranch-cost= Target RejectNegative Joined UInteger Var(mips_branch_cost) --mbranch-cost=COST Set the cost of branches to roughly COST instructions +-mbranch-cost=COST Set the cost of branches to roughly COST instructions. mbranch-likely Target Report Mask(BRANCHLIKELY) -Use Branch Likely instructions, overriding the architecture default +Use Branch Likely instructions, overriding the architecture default. mflip-mips16 Target Report Var(TARGET_FLIP_MIPS16) -Switch on/off MIPS16 ASE on alternating functions for compiler testing +Switch on/off MIPS16 ASE on alternating functions for compiler testing. mcheck-zero-division Target Report Mask(CHECK_ZERO_DIV) -Trap on integer divide by zero +Trap on integer divide by zero. mcode-readable= Target RejectNegative Joined Enum(mips_code_readable_setting) Var(mips_code_readable) Init(CODE_READABLE_YES) --mcode-readable=SETTING Specify when instructions are allowed to access code +-mcode-readable=SETTING Specify when instructions are allowed to access code. Enum Name(mips_code_readable_setting) Type(enum mips_code_readable_setting) @@ -101,27 +101,27 @@ Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO) mdivide-breaks Target Report RejectNegative Mask(DIVIDE_BREAKS) -Use branch-and-break sequences to check for integer divide by zero +Use branch-and-break sequences to check for integer divide by zero. mdivide-traps Target Report RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS) -Use trap instructions to check for integer divide by zero +Use trap instructions to check for integer divide by zero. mdmx Target Report RejectNegative Var(TARGET_MDMX) -Allow the use of MDMX instructions +Allow the use of MDMX instructions. mdouble-float Target Report RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT) -Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations +Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations. mdsp Target Report Var(TARGET_DSP) -Use MIPS-DSP instructions +Use MIPS-DSP instructions. mdspr2 Target Report Var(TARGET_DSPR2) -Use MIPS-DSP REV 2 instructions +Use MIPS-DSP REV 2 instructions. mdebug Target Var(TARGET_DEBUG_MODE) Undocumented @@ -131,91 +131,91 @@ Target Var(TARGET_DEBUG_D_MODE) Undocumented meb Target Report RejectNegative Mask(BIG_ENDIAN) -Use big-endian byte order +Use big-endian byte order. mel Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN) -Use little-endian byte order +Use little-endian byte order. membedded-data Target Report Var(TARGET_EMBEDDED_DATA) -Use ROM instead of RAM +Use ROM instead of RAM. meva Target Report Var(TARGET_EVA) -Use Enhanced Virtual Addressing instructions +Use Enhanced Virtual Addressing instructions. mexplicit-relocs Target Report Mask(EXPLICIT_RELOCS) -Use NewABI-style %reloc() assembly operators +Use NewABI-style %reloc() assembly operators. mextern-sdata Target Report Var(TARGET_EXTERN_SDATA) Init(1) -Use -G for data that is not defined by the current object +Use -G for data that is not defined by the current object. mfix-24k Target Report Var(TARGET_FIX_24K) -Work around certain 24K errata +Work around certain 24K errata. mfix-r4000 Target Report Mask(FIX_R4000) -Work around certain R4000 errata +Work around certain R4000 errata. mfix-r4400 Target Report Mask(FIX_R4400) -Work around certain R4400 errata +Work around certain R4400 errata. mfix-rm7000 Target Report Var(TARGET_FIX_RM7000) -Work around certain RM7000 errata +Work around certain RM7000 errata. mfix-r10000 Target Report Mask(FIX_R10000) -Work around certain R10000 errata +Work around certain R10000 errata. mfix-sb1 Target Report Var(TARGET_FIX_SB1) -Work around errata for early SB-1 revision 2 cores +Work around errata for early SB-1 revision 2 cores. mfix-vr4120 Target Report Var(TARGET_FIX_VR4120) -Work around certain VR4120 errata +Work around certain VR4120 errata. mfix-vr4130 Target Report Var(TARGET_FIX_VR4130) -Work around VR4130 mflo/mfhi errata +Work around VR4130 mflo/mfhi errata. mfix4300 Target Report Var(TARGET_4300_MUL_FIX) -Work around an early 4300 hardware bug +Work around an early 4300 hardware bug. mfp-exceptions Target Report Var(TARGET_FP_EXCEPTIONS) Init(1) -FP exceptions are enabled +FP exceptions are enabled. mfp32 Target Report RejectNegative InverseMask(FLOAT64) -Use 32-bit floating-point registers +Use 32-bit floating-point registers. mfpxx Target Report RejectNegative Mask(FLOATXX) -Conform to the o32 FPXX ABI +Conform to the o32 FPXX ABI. mfp64 Target Report RejectNegative Mask(FLOAT64) -Use 64-bit floating-point registers +Use 64-bit floating-point registers. mflush-func= Target RejectNegative Joined Var(mips_cache_flush_func) Init(CACHE_FLUSH_FUNC) --mflush-func=FUNC Use FUNC to flush the cache before calling stack trampolines +-mflush-func=FUNC Use FUNC to flush the cache before calling stack trampolines. mabs= Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_abs) Init(MIPS_IEEE_754_DEFAULT) --mabs=MODE Select the IEEE 754 ABS/NEG instruction execution mode +-mabs=MODE Select the IEEE 754 ABS/NEG instruction execution mode. mnan= Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_nan) Init(MIPS_IEEE_754_DEFAULT) --mnan=ENCODING Select the IEEE 754 NaN data encoding +-mnan=ENCODING Select the IEEE 754 NaN data encoding. Enum Name(mips_ieee_754_value) Type(int) @@ -229,23 +229,23 @@ Enum(mips_ieee_754_value) String(legacy) Value(MIPS_IEEE_754_LEGACY) mgp32 Target Report RejectNegative InverseMask(64BIT) -Use 32-bit general registers +Use 32-bit general registers. mgp64 Target Report RejectNegative Mask(64BIT) -Use 64-bit general registers +Use 64-bit general registers. mgpopt Target Report Var(TARGET_GPOPT) Init(1) -Use GP-relative addressing to access small data +Use GP-relative addressing to access small data. mplt Target Report Var(TARGET_PLT) -When generating -mabicalls code, allow executables to use PLTs and copy relocations +When generating -mabicalls code, allow executables to use PLTs and copy relocations. mhard-float Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI) -Allow the use of hardware floating-point ABI and instructions +Allow the use of hardware floating-point ABI and instructions. minterlink-compressed Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0) @@ -257,83 +257,83 @@ An alias for minterlink-compressed provided for backward-compatibility. mips Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_option) --mipsN Generate code for ISA level N +-mipsN Generate code for ISA level N. mips16 Target Report RejectNegative Mask(MIPS16) -Generate MIPS16 code +Generate MIPS16 code. mips3d Target Report RejectNegative Var(TARGET_MIPS3D) -Use MIPS-3D instructions +Use MIPS-3D instructions. mllsc Target Report Mask(LLSC) -Use ll, sc and sync instructions +Use ll, sc and sync instructions. mlocal-sdata Target Report Var(TARGET_LOCAL_SDATA) Init(1) -Use -G for object-local data +Use -G for object-local data. mlong-calls Target Report Var(TARGET_LONG_CALLS) -Use indirect calls +Use indirect calls. mlong32 Target Report RejectNegative InverseMask(LONG64, LONG32) -Use a 32-bit long type +Use a 32-bit long type. mlong64 Target Report RejectNegative Mask(LONG64) -Use a 64-bit long type +Use a 64-bit long type. mmcount-ra-address Target Report Var(TARGET_MCOUNT_RA_ADDRESS) -Pass the address of the ra save location to _mcount in $12 +Pass the address of the ra save location to _mcount in $12. mmemcpy Target Report Mask(MEMCPY) -Don't optimize block moves +Don't optimize block moves. mmicromips Target Report Mask(MICROMIPS) -Use microMIPS instructions +Use microMIPS instructions. mmt Target Report Var(TARGET_MT) -Allow the use of MT instructions +Allow the use of MT instructions. mno-float Target Report RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT) -Prevent the use of all floating-point operations +Prevent the use of all floating-point operations. mmcu Target Report Var(TARGET_MCU) -Use MCU instructions +Use MCU instructions. mno-flush-func Target RejectNegative -Do not use a cache-flushing function before calling stack trampolines +Do not use a cache-flushing function before calling stack trampolines. mno-mdmx Target Report RejectNegative Var(TARGET_MDMX, 0) -Do not use MDMX instructions +Do not use MDMX instructions. mno-mips16 Target Report RejectNegative InverseMask(MIPS16) -Generate normal-mode code +Generate normal-mode code. mno-mips3d Target Report RejectNegative Var(TARGET_MIPS3D, 0) -Do not use MIPS-3D instructions +Do not use MIPS-3D instructions. mpaired-single Target Report Mask(PAIRED_SINGLE_FLOAT) -Use paired-single floating-point instructions +Use paired-single floating-point instructions. mr10k-cache-barrier= Target Joined RejectNegative Enum(mips_r10k_cache_barrier_setting) Var(mips_r10k_cache_barrier) Init(R10K_CACHE_BARRIER_NONE) --mr10k-cache-barrier=SETTING Specify when r10k cache barriers should be inserted +-mr10k-cache-barrier=SETTING Specify when r10k cache barriers should be inserted. Enum Name(mips_r10k_cache_barrier_setting) Type(enum mips_r10k_cache_barrier_setting) @@ -350,71 +350,71 @@ Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE mrelax-pic-calls Target Report Mask(RELAX_PIC_CALLS) -Try to allow the linker to turn PIC calls into direct calls +Try to allow the linker to turn PIC calls into direct calls. mshared Target Report Var(TARGET_SHARED) Init(1) -When generating -mabicalls code, make the code suitable for use in shared libraries +When generating -mabicalls code, make the code suitable for use in shared libraries. msingle-float Target Report RejectNegative Mask(SINGLE_FLOAT) -Restrict the use of hardware floating-point instructions to 32-bit operations +Restrict the use of hardware floating-point instructions to 32-bit operations. msmartmips Target Report Mask(SMARTMIPS) -Use SmartMIPS instructions +Use SmartMIPS instructions. msoft-float Target Report RejectNegative Mask(SOFT_FLOAT_ABI) -Prevent the use of all hardware floating-point instructions +Prevent the use of all hardware floating-point instructions. msplit-addresses Target Report Mask(SPLIT_ADDRESSES) -Optimize lui/addiu address loads +Optimize lui/addiu address loads. msym32 Target Report Var(TARGET_SYM32) -Assume all symbols have 32-bit values +Assume all symbols have 32-bit values. msynci Target Report Mask(SYNCI) -Use synci instruction to invalidate i-cache +Use synci instruction to invalidate i-cache. mlra Target Report Var(mips_lra_flag) Init(1) Save -Use LRA instead of reload +Use LRA instead of reload. mtune= Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value) --mtune=PROCESSOR Optimize the output for PROCESSOR +-mtune=PROCESSOR Optimize the output for PROCESSOR. muninit-const-in-rodata Target Report Var(TARGET_UNINIT_CONST_IN_RODATA) -Put uninitialized constants in ROM (needs -membedded-data) +Put uninitialized constants in ROM (needs -membedded-data). mvirt Target Report Var(TARGET_VIRT) -Use Virtualization Application Specific instructions +Use Virtualization Application Specific instructions. mxpa Target Report Var(TARGET_XPA) -Use eXtended Physical Address (XPA) instructions +Use eXtended Physical Address (XPA) instructions. mvr4130-align Target Report Mask(VR4130_ALIGN) -Perform VR4130-specific alignment optimizations +Perform VR4130-specific alignment optimizations. mxgot Target Report Var(TARGET_XGOT) -Lift restrictions on GOT size +Lift restrictions on GOT size. modd-spreg Target Report Mask(ODD_SPREG) -Enable use of odd-numbered single-precision registers +Enable use of odd-numbered single-precision registers. mframe-header-opt Target Report Var(flag_frame_header_optimization) Optimization -Optimize frame header +Optimize frame header. noasmopt Driver @@ -425,7 +425,7 @@ Enable load/store bonding. mcompact-branches= Target RejectNegative JoinedOrMissing Var(mips_cb) Report Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL) -Specify the compact branch usage policy +Specify the compact branch usage policy. Enum Name(mips_cb_setting) Type(enum mips_cb_setting) diff --git a/gcc/config/mmix/mmix.opt b/gcc/config/mmix/mmix.opt index 57a7403f2d8..1093179f82a 100644 --- a/gcc/config/mmix/mmix.opt +++ b/gcc/config/mmix/mmix.opt @@ -21,48 +21,48 @@ ; FIXME: Get rid of this one. mlibfuncs Target Report Mask(LIBFUNC) -For intrinsics library: pass all parameters in registers +For intrinsics library: pass all parameters in registers. mabi=mmixware Target Report RejectNegative InverseMask(ABI_GNU) -Use register stack for parameters and return value +Use register stack for parameters and return value. mabi=gnu Target Report RejectNegative Mask(ABI_GNU) -Use call-clobbered registers for parameters and return value +Use call-clobbered registers for parameters and return value. ; FIXME: Provide a way to *load* the epsilon register. mepsilon Target Report Mask(FCMP_EPSILON) -Use epsilon-respecting floating point compare instructions +Use epsilon-respecting floating point compare instructions. mzero-extend Target Report Mask(ZERO_EXTEND) -Use zero-extending memory loads, not sign-extending ones +Use zero-extending memory loads, not sign-extending ones. mknuthdiv Target Report Mask(KNUTH_DIVISION) -Generate divide results with reminder having the same sign as the divisor (not the dividend) +Generate divide results with reminder having the same sign as the divisor (not the dividend). mtoplevel-symbols Target Report Mask(TOPLEVEL_SYMBOLS) -Prepend global symbols with \":\" (for use with PREFIX) +Prepend global symbols with \":\" (for use with PREFIX). mno-set-program-start Target Report RejectNegative -Do not provide a default start-address 0x100 of the program +Do not provide a default start-address 0x100 of the program. melf Target Report RejectNegative -Link to emit program in ELF format (rather than mmo) +Link to emit program in ELF format (rather than mmo). mbranch-predict Target Report RejectNegative Mask(BRANCH_PREDICT) -Use P-mnemonics for branches statically predicted as taken +Use P-mnemonics for branches statically predicted as taken. mno-branch-predict Target Report RejectNegative InverseMask(BRANCH_PREDICT) -Don't use P-mnemonics for branches +Don't use P-mnemonics for branches. ; We use the term "base address" since that's what Knuth uses. The base ; address goes in a global register. When addressing, it's more like @@ -76,24 +76,24 @@ Don't use P-mnemonics for branches ; should have compiled with -mno-base-addresses. mbase-addresses Target Report RejectNegative Mask(BASE_ADDRESSES) -Use addresses that allocate global registers +Use addresses that allocate global registers. mno-base-addresses Target Report RejectNegative InverseMask(BASE_ADDRESSES) -Do not use addresses that allocate global registers +Do not use addresses that allocate global registers. msingle-exit Target Report RejectNegative InverseMask(USE_RETURN_INSN) -Generate a single exit point for each function +Generate a single exit point for each function. mno-single-exit Target Report RejectNegative Mask(USE_RETURN_INSN) -Do not generate a single exit point for each function +Do not generate a single exit point for each function. mset-program-start= Target Report RejectNegative Joined -Set start-address of the program +Set start-address of the program. mset-data-start= Target Report RejectNegative Joined -Set start-address of data +Set start-address of data. diff --git a/gcc/config/mn10300/mn10300.opt b/gcc/config/mn10300/mn10300.opt index d3ac9125fe7..1ae07b0a832 100644 --- a/gcc/config/mn10300/mn10300.opt +++ b/gcc/config/mn10300/mn10300.opt @@ -27,23 +27,23 @@ enum processor_type mn10300_processor = PROCESSOR_DEFAULT mam33 Target -Target the AM33 processor +Target the AM33 processor. mam33-2 Target -Target the AM33/2.0 processor +Target the AM33/2.0 processor. mam34 Target Report -Target the AM34 processor +Target the AM34 processor. mtune= Target RejectNegative Joined Var(mn10300_tune_string) -Tune code for the given processor +Tune code for the given processor. mmult-bug Target Report Mask(MULT_BUG) -Work around hardware multiply bug +Work around hardware multiply bug. ; Ignored by the compiler mno-crt0 @@ -52,16 +52,16 @@ Target RejectNegative ; Ignored by the compiler mrelax Target RejectNegative -Enable linker relaxations +Enable linker relaxations. mreturn-pointer-on-d0 Target Report Mask(PTR_A0D0) -Return pointers in both a0 and d0 +Return pointers in both a0 and d0. mliw Target Report Mask(ALLOW_LIW) -Allow gcc to generate LIW instructions +Allow gcc to generate LIW instructions. msetlb Target Report Mask(ALLOW_SETLB) -Allow gcc to generate the SETLB and Lcc instructions +Allow gcc to generate the SETLB and Lcc instructions. diff --git a/gcc/config/moxie/moxie.opt b/gcc/config/moxie/moxie.opt index 199180b0420..2fbc9c11460 100644 --- a/gcc/config/moxie/moxie.opt +++ b/gcc/config/moxie/moxie.opt @@ -20,15 +20,15 @@ meb Target RejectNegative Report InverseMask(LITTLE_ENDIAN) -Generate big-endian code +Generate big-endian code. mel Target RejectNegative Report Mask(LITTLE_ENDIAN) -Generate little-endian code +Generate little-endian code. mmul.x Target Report Mask(HAS_MULX) -Enable MUL.X and UMUL.X instructions +Enable MUL.X and UMUL.X instructions. ; Ignored by the compiler mno-crt0 diff --git a/gcc/config/msp430/msp430.opt b/gcc/config/msp430/msp430.opt index e055f61069d..aa1b39ed4bc 100644 --- a/gcc/config/msp430/msp430.opt +++ b/gcc/config/msp430/msp430.opt @@ -1,10 +1,10 @@ msim Target -Use simulator runtime +Use simulator runtime. masm-hex Target Mask(ASM_HEX) -Force assembly output to always use hex constants +Force assembly output to always use hex constants. mmcu= Target Report ToLower Joined RejectNegative Var(target_mcu) @@ -12,19 +12,19 @@ Specify the MCU to build for. mcpu= Target Report Joined RejectNegative Var(target_cpu) -Specify the ISA to build for: msp430, msp430x, msp430xv2 +Specify the ISA to build for: msp430, msp430x, msp430xv2. mlarge Target Report Mask(LARGE) RejectNegative -Select large model - 20-bit addresses/pointers +Select large model - 20-bit addresses/pointers. msmall Target Report InverseMask(LARGE) RejectNegative -Select small model - 16-bit addresses/pointers (default) +Select small model - 16-bit addresses/pointers (default). mrelax Target Report -Optimize opcode sizes at link time +Optimize opcode sizes at link time. mOs Target Undocumented Mask(OPT_SPACE) @@ -38,7 +38,7 @@ config/msp430/msp430-opts.h mhwmult= Target Joined RejectNegative Report ToLower Var(msp430_hwmult_type) Enum(msp430_hwmult_types) Init(AUTO) -Specify the type of hardware multiply to support +Specify the type of hardware multiply to support. Enum Name(msp430_hwmult_types) Type(enum msp430_hwmult_types) @@ -60,11 +60,11 @@ Enum(msp430_hwmult_types) String(f5series) Value(F5SERIES) mcode-region= Target Joined RejectNegative Report ToLower Var(msp430_code_region) Enum(msp430_regions) Init(ANY) -Specify whether functions should be placed into low or high memory +Specify whether functions should be placed into low or high memory. mdata-region= Target Joined RejectNegative Report ToLower Var(msp430_data_region) Enum(msp430_regions) Init(ANY) -Specify whether variables should be placed into low or high memory +Specify whether variables should be placed into low or high memory. Enum Name(msp430_regions) Type(enum msp430_regions) diff --git a/gcc/config/nios2/elf.opt b/gcc/config/nios2/elf.opt index c0c9623d09d..2887dca098d 100644 --- a/gcc/config/nios2/elf.opt +++ b/gcc/config/nios2/elf.opt @@ -23,16 +23,16 @@ msmallc Target Report RejectNegative -Link with a limited version of the C library +Link with a limited version of the C library. msys-lib= Target RejectNegative Joined Var(nios2_sys_lib_string) -Name of system library to link against +Name of system library to link against. msys-crt0= Target RejectNegative Joined Var(nios2_sys_crt0_string) -Name of the startfile +Name of the startfile. mhal Target Report RejectNegative -Link with HAL BSP +Link with HAL BSP. diff --git a/gcc/config/nios2/nios2.opt b/gcc/config/nios2/nios2.opt index 1e151f7b796..41afe4d87ab 100644 --- a/gcc/config/nios2/nios2.opt +++ b/gcc/config/nios2/nios2.opt @@ -32,31 +32,31 @@ int saved_custom_code_index[256] mhw-div Target Report Mask(HAS_DIV) -Enable DIV, DIVU +Enable DIV, DIVU. mhw-mul Target Report Mask(HAS_MUL) -Enable MUL instructions +Enable MUL instructions. mhw-mulx Target Report Mask(HAS_MULX) -Enable MULX instructions, assume fast shifter +Enable MULX instructions, assume fast shifter. mfast-sw-div Target Report Mask(FAST_SW_DIV) -Use table based fast divide (default at -O3) +Use table based fast divide (default at -O3). mbypass-cache Target Report Mask(BYPASS_CACHE) -All memory accesses use I/O load/store instructions +All memory accesses use I/O load/store instructions. mno-cache-volatile Target Report RejectNegative Mask(BYPASS_CACHE_VOLATILE) -Volatile memory accesses use I/O load/store instructions +Volatile memory accesses use I/O load/store instructions. mcache-volatile Target Report RejectNegative Undocumented InverseMask(BYPASS_CACHE_VOLATILE) -Volatile memory accesses do not use I/O load/store instructions +Volatile memory accesses do not use I/O load/store instructions. mgpopt= Target RejectNegative Joined Enum(nios2_gpopt_type) Var(nios2_gpopt_option) Init(gpopt_unspecified) @@ -91,479 +91,479 @@ Equivalent to -mgpopt=none. meb Target Report RejectNegative Mask(BIG_ENDIAN) -Use big-endian byte order +Use big-endian byte order. mel Target Report RejectNegative InverseMask(BIG_ENDIAN) -Use little-endian byte order +Use little-endian byte order. mcustom-fpu-cfg= Target RejectNegative Joined Var(nios2_custom_fpu_cfg_string) -Floating point custom instruction configuration name +Floating point custom instruction configuration name. mno-custom-ftruncds Target Report RejectNegative Var(nios2_custom_ftruncds, -1) -Do not use the ftruncds custom instruction +Do not use the ftruncds custom instruction. mcustom-ftruncds= Target Report RejectNegative Joined UInteger Var(nios2_custom_ftruncds) Init(-1) -Integer id (N) of ftruncds custom instruction +Integer id (N) of ftruncds custom instruction. mno-custom-fextsd Target Report RejectNegative Var(nios2_custom_fextsd, -1) -Do not use the fextsd custom instruction +Do not use the fextsd custom instruction. mcustom-fextsd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fextsd) Init(-1) -Integer id (N) of fextsd custom instruction +Integer id (N) of fextsd custom instruction. mno-custom-fixdu Target Report RejectNegative Var(nios2_custom_fixdu, -1) -Do not use the fixdu custom instruction +Do not use the fixdu custom instruction. mcustom-fixdu= Target Report RejectNegative Joined UInteger Var(nios2_custom_fixdu) Init(-1) -Integer id (N) of fixdu custom instruction +Integer id (N) of fixdu custom instruction. mno-custom-fixdi Target Report RejectNegative Var(nios2_custom_fixdi, -1) -Do not use the fixdi custom instruction +Do not use the fixdi custom instruction. mcustom-fixdi= Target Report RejectNegative Joined UInteger Var(nios2_custom_fixdi) Init(-1) -Integer id (N) of fixdi custom instruction +Integer id (N) of fixdi custom instruction. mno-custom-fixsu Target Report RejectNegative Var(nios2_custom_fixsu, -1) -Do not use the fixsu custom instruction +Do not use the fixsu custom instruction. mcustom-fixsu= Target Report RejectNegative Joined UInteger Var(nios2_custom_fixsu) Init(-1) -Integer id (N) of fixsu custom instruction +Integer id (N) of fixsu custom instruction. mno-custom-fixsi Target Report RejectNegative Var(nios2_custom_fixsi, -1) -Do not use the fixsi custom instruction +Do not use the fixsi custom instruction. mcustom-fixsi= Target Report RejectNegative Joined UInteger Var(nios2_custom_fixsi) Init(-1) -Integer id (N) of fixsi custom instruction +Integer id (N) of fixsi custom instruction. mno-custom-floatud Target Report RejectNegative Var(nios2_custom_floatud, -1) -Do not use the floatud custom instruction +Do not use the floatud custom instruction. mcustom-floatud= Target Report RejectNegative Joined UInteger Var(nios2_custom_floatud) Init(-1) -Integer id (N) of floatud custom instruction +Integer id (N) of floatud custom instruction. mno-custom-floatid Target Report RejectNegative Var(nios2_custom_floatid, -1) -Do not use the floatid custom instruction +Do not use the floatid custom instruction. mcustom-floatid= Target Report RejectNegative Joined UInteger Var(nios2_custom_floatid) Init(-1) -Integer id (N) of floatid custom instruction +Integer id (N) of floatid custom instruction. mno-custom-floatus Target Report RejectNegative Var(nios2_custom_floatus, -1) -Do not use the floatus custom instruction +Do not use the floatus custom instruction. mcustom-floatus= Target Report RejectNegative Joined UInteger Var(nios2_custom_floatus) Init(-1) -Integer id (N) of floatus custom instruction +Integer id (N) of floatus custom instruction. mno-custom-floatis Target Report RejectNegative Var(nios2_custom_floatis, -1) -Do not use the floatis custom instruction +Do not use the floatis custom instruction. mcustom-floatis= Target Report RejectNegative Joined UInteger Var(nios2_custom_floatis) Init(-1) -Integer id (N) of floatis custom instruction +Integer id (N) of floatis custom instruction. mno-custom-fcmpned Target Report RejectNegative Var(nios2_custom_fcmpned, -1) -Do not use the fcmpned custom instruction +Do not use the fcmpned custom instruction. mcustom-fcmpned= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpned) Init(-1) -Integer id (N) of fcmpned custom instruction +Integer id (N) of fcmpned custom instruction. mno-custom-fcmpeqd Target Report RejectNegative Var(nios2_custom_fcmpeqd, -1) -Do not use the fcmpeqd custom instruction +Do not use the fcmpeqd custom instruction. mcustom-fcmpeqd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpeqd) Init(-1) -Integer id (N) of fcmpeqd custom instruction +Integer id (N) of fcmpeqd custom instruction. mno-custom-fcmpged Target Report RejectNegative Var(nios2_custom_fcmpged, -1) -Do not use the fcmpged custom instruction +Do not use the fcmpged custom instruction. mcustom-fcmpged= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpged) Init(-1) -Integer id (N) of fcmpged custom instruction +Integer id (N) of fcmpged custom instruction. mno-custom-fcmpgtd Target Report RejectNegative Var(nios2_custom_fcmpgtd, -1) -Do not use the fcmpgtd custom instruction +Do not use the fcmpgtd custom instruction. mcustom-fcmpgtd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpgtd) Init(-1) -Integer id (N) of fcmpgtd custom instruction +Integer id (N) of fcmpgtd custom instruction. mno-custom-fcmpled Target Report RejectNegative Var(nios2_custom_fcmpled, -1) -Do not use the fcmpled custom instruction +Do not use the fcmpled custom instruction. mcustom-fcmpled= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpled) Init(-1) -Integer id (N) of fcmpled custom instruction +Integer id (N) of fcmpled custom instruction. mno-custom-fcmpltd Target Report RejectNegative Var(nios2_custom_fcmpltd, -1) -Do not use the fcmpltd custom instruction +Do not use the fcmpltd custom instruction. mcustom-fcmpltd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpltd) Init(-1) -Integer id (N) of fcmpltd custom instruction +Integer id (N) of fcmpltd custom instruction. mno-custom-flogd Target Report RejectNegative Var(nios2_custom_flogd, -1) -Do not use the flogd custom instruction +Do not use the flogd custom instruction. mcustom-flogd= Target Report RejectNegative Joined UInteger Var(nios2_custom_flogd) Init(-1) -Integer id (N) of flogd custom instruction +Integer id (N) of flogd custom instruction. mno-custom-fexpd Target Report RejectNegative Var(nios2_custom_fexpd, -1) -Do not use the fexpd custom instruction +Do not use the fexpd custom instruction. mcustom-fexpd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fexpd) Init(-1) -Integer id (N) of fexpd custom instruction +Integer id (N) of fexpd custom instruction. mno-custom-fatand Target Report RejectNegative Var(nios2_custom_fatand, -1) -Do not use the fatand custom instruction +Do not use the fatand custom instruction. mcustom-fatand= Target Report RejectNegative Joined UInteger Var(nios2_custom_fatand) Init(-1) -Integer id (N) of fatand custom instruction +Integer id (N) of fatand custom instruction. mno-custom-ftand Target Report RejectNegative Var(nios2_custom_ftand, -1) -Do not use the ftand custom instruction +Do not use the ftand custom instruction. mcustom-ftand= Target Report RejectNegative Joined UInteger Var(nios2_custom_ftand) Init(-1) -Integer id (N) of ftand custom instruction +Integer id (N) of ftand custom instruction. mno-custom-fsind Target Report RejectNegative Var(nios2_custom_fsind, -1) -Do not use the fsind custom instruction +Do not use the fsind custom instruction. mcustom-fsind= Target Report RejectNegative Joined UInteger Var(nios2_custom_fsind) Init(-1) -Integer id (N) of fsind custom instruction +Integer id (N) of fsind custom instruction. mno-custom-fcosd Target Report RejectNegative Var(nios2_custom_fcosd, -1) -Do not use the fcosd custom instruction +Do not use the fcosd custom instruction. mcustom-fcosd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcosd) Init(-1) -Integer id (N) of fcosd custom instruction +Integer id (N) of fcosd custom instruction. mno-custom-fsqrtd Target Report RejectNegative Var(nios2_custom_fsqrtd, -1) -Do not use the fsqrtd custom instruction +Do not use the fsqrtd custom instruction. mcustom-fsqrtd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fsqrtd) Init(-1) -Integer id (N) of fsqrtd custom instruction +Integer id (N) of fsqrtd custom instruction. mno-custom-fabsd Target Report RejectNegative Var(nios2_custom_fabsd, -1) -Do not use the fabsd custom instruction +Do not use the fabsd custom instruction. mcustom-fabsd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fabsd) Init(-1) -Integer id (N) of fabsd custom instruction +Integer id (N) of fabsd custom instruction. mno-custom-fnegd Target Report RejectNegative Var(nios2_custom_fnegd, -1) -Do not use the fnegd custom instruction +Do not use the fnegd custom instruction. mcustom-fnegd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fnegd) Init(-1) -Integer id (N) of fnegd custom instruction +Integer id (N) of fnegd custom instruction. mno-custom-fmaxd Target Report RejectNegative Var(nios2_custom_fmaxd, -1) -Do not use the fmaxd custom instruction +Do not use the fmaxd custom instruction. mcustom-fmaxd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fmaxd) Init(-1) -Integer id (N) of fmaxd custom instruction +Integer id (N) of fmaxd custom instruction. mno-custom-fmind Target Report RejectNegative Var(nios2_custom_fmind, -1) -Do not use the fmind custom instruction +Do not use the fmind custom instruction. mcustom-fmind= Target Report RejectNegative Joined UInteger Var(nios2_custom_fmind) Init(-1) -Integer id (N) of fmind custom instruction +Integer id (N) of fmind custom instruction. mno-custom-fdivd Target Report RejectNegative Var(nios2_custom_fdivd, -1) -Do not use the fdivd custom instruction +Do not use the fdivd custom instruction. mcustom-fdivd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fdivd) Init(-1) -Integer id (N) of fdivd custom instruction +Integer id (N) of fdivd custom instruction. mno-custom-fmuld Target Report RejectNegative Var(nios2_custom_fmuld, -1) -Do not use the fmuld custom instruction +Do not use the fmuld custom instruction. mcustom-fmuld= Target Report RejectNegative Joined UInteger Var(nios2_custom_fmuld) Init(-1) -Integer id (N) of fmuld custom instruction +Integer id (N) of fmuld custom instruction. mno-custom-fsubd Target Report RejectNegative Var(nios2_custom_fsubd, -1) -Do not use the fsubd custom instruction +Do not use the fsubd custom instruction. mcustom-fsubd= Target Report RejectNegative Joined UInteger Var(nios2_custom_fsubd) Init(-1) -Integer id (N) of fsubd custom instruction +Integer id (N) of fsubd custom instruction. mno-custom-faddd Target Report RejectNegative Var(nios2_custom_faddd, -1) -Do not use the faddd custom instruction +Do not use the faddd custom instruction. mcustom-faddd= Target Report RejectNegative Joined UInteger Var(nios2_custom_faddd) Init(-1) -Integer id (N) of faddd custom instruction +Integer id (N) of faddd custom instruction. mno-custom-fcmpnes Target Report RejectNegative Var(nios2_custom_fcmpnes, -1) -Do not use the fcmpnes custom instruction +Do not use the fcmpnes custom instruction. mcustom-fcmpnes= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpnes) Init(-1) -Integer id (N) of fcmpnes custom instruction +Integer id (N) of fcmpnes custom instruction. mno-custom-fcmpeqs Target Report RejectNegative Var(nios2_custom_fcmpeqs, -1) -Do not use the fcmpeqs custom instruction +Do not use the fcmpeqs custom instruction. mcustom-fcmpeqs= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpeqs) Init(-1) -Integer id (N) of fcmpeqs custom instruction +Integer id (N) of fcmpeqs custom instruction. mno-custom-fcmpges Target Report RejectNegative Var(nios2_custom_fcmpges, -1) -Do not use the fcmpges custom instruction +Do not use the fcmpges custom instruction. mcustom-fcmpges= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpges) Init(-1) -Integer id (N) of fcmpges custom instruction +Integer id (N) of fcmpges custom instruction. mno-custom-fcmpgts Target Report RejectNegative Var(nios2_custom_fcmpgts, -1) -Do not use the fcmpgts custom instruction +Do not use the fcmpgts custom instruction. mcustom-fcmpgts= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpgts) Init(-1) -Integer id (N) of fcmpgts custom instruction +Integer id (N) of fcmpgts custom instruction. mno-custom-fcmples Target Report RejectNegative Var(nios2_custom_fcmples, -1) -Do not use the fcmples custom instruction +Do not use the fcmples custom instruction. mcustom-fcmples= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmples) Init(-1) -Integer id (N) of fcmples custom instruction +Integer id (N) of fcmples custom instruction. mno-custom-fcmplts Target Report RejectNegative Var(nios2_custom_fcmplts, -1) -Do not use the fcmplts custom instruction +Do not use the fcmplts custom instruction. mcustom-fcmplts= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmplts) Init(-1) -Integer id (N) of fcmplts custom instruction +Integer id (N) of fcmplts custom instruction. mno-custom-flogs Target Report RejectNegative Var(nios2_custom_flogs, -1) -Do not use the flogs custom instruction +Do not use the flogs custom instruction. mcustom-flogs= Target Report RejectNegative Joined UInteger Var(nios2_custom_flogs) Init(-1) -Integer id (N) of flogs custom instruction +Integer id (N) of flogs custom instruction. mno-custom-fexps Target Report RejectNegative Var(nios2_custom_fexps, -1) -Do not use the fexps custom instruction +Do not use the fexps custom instruction. mcustom-fexps= Target Report RejectNegative Joined UInteger Var(nios2_custom_fexps) Init(-1) -Integer id (N) of fexps custom instruction +Integer id (N) of fexps custom instruction. mno-custom-fatans Target Report RejectNegative Var(nios2_custom_fatans, -1) -Do not use the fatans custom instruction +Do not use the fatans custom instruction. mcustom-fatans= Target Report RejectNegative Joined UInteger Var(nios2_custom_fatans) Init(-1) -Integer id (N) of fatans custom instruction +Integer id (N) of fatans custom instruction. mno-custom-ftans Target Report RejectNegative Var(nios2_custom_ftans, -1) -Do not use the ftans custom instruction +Do not use the ftans custom instruction. mcustom-ftans= Target Report RejectNegative Joined UInteger Var(nios2_custom_ftans) Init(-1) -Integer id (N) of ftans custom instruction +Integer id (N) of ftans custom instruction. mno-custom-fsins Target Report RejectNegative Var(nios2_custom_fsins, -1) -Do not use the fsins custom instruction +Do not use the fsins custom instruction. mcustom-fsins= Target Report RejectNegative Joined UInteger Var(nios2_custom_fsins) Init(-1) -Integer id (N) of fsins custom instruction +Integer id (N) of fsins custom instruction. mno-custom-fcoss Target Report RejectNegative Var(nios2_custom_fcoss, -1) -Do not use the fcoss custom instruction +Do not use the fcoss custom instruction. mcustom-fcoss= Target Report RejectNegative Joined UInteger Var(nios2_custom_fcoss) Init(-1) -Integer id (N) of fcoss custom instruction +Integer id (N) of fcoss custom instruction. mno-custom-fsqrts Target Report RejectNegative Var(nios2_custom_fsqrts, -1) -Do not use the fsqrts custom instruction +Do not use the fsqrts custom instruction. mcustom-fsqrts= Target Report RejectNegative Joined UInteger Var(nios2_custom_fsqrts) Init(-1) -Integer id (N) of fsqrts custom instruction +Integer id (N) of fsqrts custom instruction. mno-custom-fabss Target Report RejectNegative Var(nios2_custom_fabss, -1) -Do not use the fabss custom instr +Do not use the fabss custom instr. mcustom-fabss= Target Report RejectNegative Joined UInteger Var(nios2_custom_fabss) Init(-1) -Integer id (N) of fabss custom instruction +Integer id (N) of fabss custom instruction. mno-custom-fnegs Target Report RejectNegative Var(nios2_custom_fnegs, -1) -Do not use the fnegs custom instruction +Do not use the fnegs custom instruction. mcustom-fnegs= Target Report RejectNegative Joined UInteger Var(nios2_custom_fnegs) Init(-1) -Integer id (N) of fnegs custom instruction +Integer id (N) of fnegs custom instruction. mno-custom-fmaxs Target Report RejectNegative Var(nios2_custom_fmaxs, -1) -Do not use the fmaxs custom instruction +Do not use the fmaxs custom instruction. mcustom-fmaxs= Target Report RejectNegative Joined UInteger Var(nios2_custom_fmaxs) Init(-1) -Integer id (N) of fmaxs custom instruction +Integer id (N) of fmaxs custom instruction. mno-custom-fmins Target Report RejectNegative Var(nios2_custom_fmins, -1) -Do not use the fmins custom instruction +Do not use the fmins custom instruction. mcustom-fmins= Target Report RejectNegative Joined UInteger Var(nios2_custom_fmins) Init(-1) -Integer id (N) of fmins custom instruction +Integer id (N) of fmins custom instruction. mno-custom-fdivs Target Report RejectNegative Var(nios2_custom_fdivs, -1) -Do not use the fdivs custom instruction +Do not use the fdivs custom instruction. mcustom-fdivs= Target Report RejectNegative Joined UInteger Var(nios2_custom_fdivs) Init(-1) -Integer id (N) of fdivs custom instruction +Integer id (N) of fdivs custom instruction. mno-custom-fmuls Target Report RejectNegative Var(nios2_custom_fmuls, -1) -Do not use the fmuls custom instruction +Do not use the fmuls custom instruction. mcustom-fmuls= Target Report RejectNegative Joined UInteger Var(nios2_custom_fmuls) Init(-1) -Integer id (N) of fmuls custom instruction +Integer id (N) of fmuls custom instruction. mno-custom-fsubs Target Report RejectNegative Var(nios2_custom_fsubs, -1) -Do not use the fsubs custom instruction +Do not use the fsubs custom instruction. mcustom-fsubs= Target Report RejectNegative Joined UInteger Var(nios2_custom_fsubs) Init(-1) -Integer id (N) of fsubs custom instruction +Integer id (N) of fsubs custom instruction. mno-custom-fadds Target Report RejectNegative Var(nios2_custom_fadds, -1) -Do not use the fadds custom instruction +Do not use the fadds custom instruction. mcustom-fadds= Target Report RejectNegative Joined UInteger Var(nios2_custom_fadds) Init(-1) -Integer id (N) of fadds custom instruction +Integer id (N) of fadds custom instruction. mno-custom-frdy Target Report RejectNegative Var(nios2_custom_frdy, -1) -Do not use the frdy custom instruction +Do not use the frdy custom instruction. mcustom-frdy= Target Report RejectNegative Joined UInteger Var(nios2_custom_frdy) Init(-1) -Integer id (N) of frdy custom instruction +Integer id (N) of frdy custom instruction. mno-custom-frdxhi Target Report RejectNegative Var(nios2_custom_frdxhi, -1) -Do not use the frdxhi custom instruction +Do not use the frdxhi custom instruction. mcustom-frdxhi= Target Report RejectNegative Joined UInteger Var(nios2_custom_frdxhi) Init(-1) -Integer id (N) of frdxhi custom instruction +Integer id (N) of frdxhi custom instruction. mno-custom-frdxlo Target Report RejectNegative Var(nios2_custom_frdxlo, -1) -Do not use the frdxlo custom instruction +Do not use the frdxlo custom instruction. mcustom-frdxlo= Target Report RejectNegative Joined UInteger Var(nios2_custom_frdxlo) Init(-1) -Integer id (N) of frdxlo custom instruction +Integer id (N) of frdxlo custom instruction. mno-custom-fwry Target Report RejectNegative Var(nios2_custom_fwry, -1) -Do not use the fwry custom instruction +Do not use the fwry custom instruction. mcustom-fwry= Target Report RejectNegative Joined UInteger Var(nios2_custom_fwry) Init(-1) -Integer id (N) of fwry custom instruction +Integer id (N) of fwry custom instruction. mno-custom-fwrx Target Report RejectNegative Var(nios2_custom_fwrx, -1) -Do not use the fwrx custom instruction +Do not use the fwrx custom instruction. mcustom-fwrx= Target Report RejectNegative Joined UInteger Var(nios2_custom_fwrx) Init(-1) -Integer id (N) of fwrx custom instruction +Integer id (N) of fwrx custom instruction. mno-custom-round Target Report RejectNegative Var(nios2_custom_round, -1) -Do not use the round custom instruction +Do not use the round custom instruction. mcustom-round= Target Report RejectNegative Joined UInteger Var(nios2_custom_round) Init(-1) -Integer id (N) of round custom instruction +Integer id (N) of round custom instruction. march= Target RejectNegative Joined Enum(nios2_arch_type) Var(nios2_arch_option) Init(ARCH_R1) @@ -581,8 +581,8 @@ Enum(nios2_arch_type) String(r2) Value(ARCH_R2) mbmx Target Report Mask(HAS_BMX) -Enable generation of R2 BMX instructions +Enable generation of R2 BMX instructions. mcdx Target Report Mask(HAS_CDX) -Enable generation of R2 CDX instructions +Enable generation of R2 CDX instructions. diff --git a/gcc/config/nvptx/nvptx.opt b/gcc/config/nvptx/nvptx.opt index 249a61d3d74..80170465bea 100644 --- a/gcc/config/nvptx/nvptx.opt +++ b/gcc/config/nvptx/nvptx.opt @@ -19,11 +19,11 @@ m32 Target Report RejectNegative InverseMask(ABI64) -Generate code for a 32-bit ABI +Generate code for a 32-bit ABI. m64 Target Report RejectNegative Mask(ABI64) -Generate code for a 64-bit ABI +Generate code for a 64-bit ABI. mmainkernel Target Report RejectNegative diff --git a/gcc/config/pa/pa-hpux.opt b/gcc/config/pa/pa-hpux.opt index 528c921c099..1ce6998a82c 100644 --- a/gcc/config/pa/pa-hpux.opt +++ b/gcc/config/pa/pa-hpux.opt @@ -24,15 +24,15 @@ int flag_pa_unix = TARGET_HPUX_11_31 ? 2003 : TARGET_HPUX_11_11 ? 1998 : TARGET_ msio Target RejectNegative Mask(SIO) -Generate cpp defines for server IO +Generate cpp defines for server IO. munix=93 Target RejectNegative Var(flag_pa_unix, 1993) -Specify UNIX standard for predefines and linking +Specify UNIX standard for predefines and linking. mwsio Target RejectNegative InverseMask(SIO) -Generate cpp defines for workstation IO +Generate cpp defines for workstation IO. nolibdld Driver diff --git a/gcc/config/pa/pa-hpux1010.opt b/gcc/config/pa/pa-hpux1010.opt index 82192cd299c..0ae6224d688 100644 --- a/gcc/config/pa/pa-hpux1010.opt +++ b/gcc/config/pa/pa-hpux1010.opt @@ -20,4 +20,4 @@ munix=95 Target RejectNegative Var(flag_pa_unix, 1995) -Specify UNIX standard for predefines and linking +Specify UNIX standard for predefines and linking. diff --git a/gcc/config/pa/pa-hpux1111.opt b/gcc/config/pa/pa-hpux1111.opt index 7f5c7b9f3f4..6623182a23e 100644 --- a/gcc/config/pa/pa-hpux1111.opt +++ b/gcc/config/pa/pa-hpux1111.opt @@ -20,4 +20,4 @@ munix=98 Target RejectNegative Var(flag_pa_unix, 1998) -Specify UNIX standard for predefines and linking +Specify UNIX standard for predefines and linking. diff --git a/gcc/config/pa/pa-hpux1131.opt b/gcc/config/pa/pa-hpux1131.opt index 717c5531121..fefd441d033 100644 --- a/gcc/config/pa/pa-hpux1131.opt +++ b/gcc/config/pa/pa-hpux1131.opt @@ -20,4 +20,4 @@ munix=2003 Target RejectNegative Var(flag_pa_unix, 2003) -Specify UNIX standard for predefines and linking +Specify UNIX standard for predefines and linking. diff --git a/gcc/config/pa/pa.opt b/gcc/config/pa/pa.opt index 57c9c5e67ac..055c5697e55 100644 --- a/gcc/config/pa/pa.opt +++ b/gcc/config/pa/pa.opt @@ -27,15 +27,15 @@ enum processor_type pa_cpu = TARGET_SCHED_DEFAULT march=1.0 Target RejectNegative -Generate PA1.0 code +Generate PA1.0 code. march=1.1 Target RejectNegative -Generate PA1.1 code +Generate PA1.1 code. march=2.0 Target RejectNegative -Generate PA2.0 code (requires binutils 2.10 or later) +Generate PA2.0 code (requires binutils 2.10 or later). mbig-switch Target Ignore @@ -43,23 +43,23 @@ Does nothing. Preserved for backward compatibility. mdisable-fpregs Target Report Mask(DISABLE_FPREGS) -Disable FP regs +Disable FP regs. mdisable-indexing Target Report Mask(DISABLE_INDEXING) -Disable indexed addressing +Disable indexed addressing. mfast-indirect-calls Target Report Mask(FAST_INDIRECT_CALLS) -Generate fast indirect calls +Generate fast indirect calls. mfixed-range= Target RejectNegative Joined Var(pa_deferred_options) Defer -Specify range of registers to make fixed +Specify range of registers to make fixed. mgas Target Report Mask(GAS) -Assume code will be assembled by GAS +Assume code will be assembled by GAS. mjump-in-delay Target Ignore @@ -68,43 +68,43 @@ Does nothing. Preserved for backward compatibility. ;; Not used by gcc mlinker-opt Target RejectNegative -Enable linker optimizations +Enable linker optimizations. mlong-calls Target Report Mask(LONG_CALLS) -Always generate long calls +Always generate long calls. mlong-load-store Target Report Mask(LONG_LOAD_STORE) -Emit long load/store sequences +Emit long load/store sequences. mnosnake Target RejectNegative -Generate PA1.0 code +Generate PA1.0 code. mno-space-regs Target RejectNegative Report Mask(NO_SPACE_REGS) -Disable space regs +Disable space regs. mpa-risc-1-0 Target RejectNegative -Generate PA1.0 code +Generate PA1.0 code. mpa-risc-1-1 Target RejectNegative Mask(PA_11) -Generate PA1.1 code +Generate PA1.1 code. mpa-risc-2-0 Target RejectNegative Mask(PA_20) -Generate PA2.0 code (requires binutils 2.10 or later) +Generate PA2.0 code (requires binutils 2.10 or later). mportable-runtime Target Report Mask(PORTABLE_RUNTIME) -Use portable calling conventions +Use portable calling conventions. mschedule= Target RejectNegative Joined Enum(pa_schedule) Var(pa_cpu) -Specify CPU for scheduling purposes. Valid arguments are 700, 7100, 7100LC, 7200, 7300, and 8000 +Specify CPU for scheduling purposes. Valid arguments are 700, 7100, 7100LC, 7200, 7300, and 8000. Enum Name(pa_schedule) Type(enum processor_type) @@ -129,12 +129,12 @@ Enum(pa_schedule) String(7300) Value(PROCESSOR_7300) msoft-float Target Report Mask(SOFT_FLOAT) -Use software floating point +Use software floating point. msnake Target RejectNegative -Generate PA1.1 code +Generate PA1.1 code. mspace-regs Target RejectNegative Report InverseMask(NO_SPACE_REGS) -Do not disable space regs +Do not disable space regs. diff --git a/gcc/config/pa/pa64-hpux.opt b/gcc/config/pa/pa64-hpux.opt index d4e39465e6b..8e65a41b971 100644 --- a/gcc/config/pa/pa64-hpux.opt +++ b/gcc/config/pa/pa64-hpux.opt @@ -20,8 +20,8 @@ mgnu-ld Target RejectNegative Mask(GNU_LD) -Assume code will be linked by GNU ld +Assume code will be linked by GNU ld. mhp-ld Target RejectNegative InverseMask(GNU_LD) -Assume code will be linked by HP ld +Assume code will be linked by HP ld. diff --git a/gcc/config/pdp11/pdp11.opt b/gcc/config/pdp11/pdp11.opt index 8fab76a2011..ff27a9f4b42 100644 --- a/gcc/config/pdp11/pdp11.opt +++ b/gcc/config/pdp11/pdp11.opt @@ -20,68 +20,68 @@ m10 Target RejectNegative -Generate code for an 11/10 +Generate code for an 11/10. m40 Target Report Mask(40) -Generate code for an 11/40 +Generate code for an 11/40. m45 Target Report Mask(45) -Generate code for an 11/45 +Generate code for an 11/45. mac0 Target Report Mask(AC0) -Return floating-point results in ac0 (fr0 in Unix assembler syntax) +Return floating-point results in ac0 (fr0 in Unix assembler syntax). mbcopy Target RejectNegative Report Mask(BCOPY) -Do not use inline patterns for copying memory +Do not use inline patterns for copying memory. mbcopy-builtin Target RejectNegative Report InverseMask(BCOPY, BCOPY_BUILTIN) -Use inline patterns for copying memory +Use inline patterns for copying memory. mbranch-cheap Target RejectNegative Report InverseMask(BRANCH_EXPENSIVE, BRANCH_CHEAP) -Do not pretend that branches are expensive +Do not pretend that branches are expensive. mbranch-expensive Target RejectNegative Report Mask(BRANCH_EXPENSIVE) -Pretend that branches are expensive +Pretend that branches are expensive. mdec-asm Target RejectNegative Report InverseMask(UNIX_ASM) -Use the DEC assembler syntax +Use the DEC assembler syntax. mfloat32 Target Report Mask(FLOAT32) -Use 32 bit float +Use 32 bit float. mfloat64 Target Report InverseMask(FLOAT32, FLOAT64) -Use 64 bit float +Use 64 bit float. mfpu Target RejectNegative Report Mask(FPU) -Use hardware floating point +Use hardware floating point. mint16 Target Report InverseMask(INT32, INT16) -Use 16 bit int +Use 16 bit int. mint32 Target Report Mask(INT32) -Use 32 bit int +Use 32 bit int. msoft-float Target RejectNegative Report InverseMask(FPU, SOFT_FLOAT) -Do not use hardware floating point +Do not use hardware floating point. msplit Target Report Mask(SPLIT) -Target has split I&D +Target has split I&D. munix-asm Target RejectNegative Report Mask(UNIX_ASM) -Use UNIX assembler syntax +Use UNIX assembler syntax. diff --git a/gcc/config/rl78/rl78.opt b/gcc/config/rl78/rl78.opt index 80b894a6e67..9d7292b2528 100644 --- a/gcc/config/rl78/rl78.opt +++ b/gcc/config/rl78/rl78.opt @@ -74,19 +74,19 @@ Enum(rl78_cpu_types) String(rl78) Value(CPU_G14) mg10 Target RejectNegative Report Alias(mcpu=, g10) -Alias for -mcpu=g10 +Alias for -mcpu=g10. mg13 Target RejectNegative Report Alias(mcpu=, g13) -Alias for -mcpu=g13 +Alias for -mcpu=g13. mg14 Target RejectNegative Report Alias(mcpu=, g14) -Alias for -mcpu=g14 +Alias for -mcpu=g14. mrl78 Target RejectNegative Report Alias(mcpu=, g14) -Alias for -mcpu=g14 +Alias for -mcpu=g14. mes0 Target Mask(ES0) diff --git a/gcc/config/rs6000/476.opt b/gcc/config/rs6000/476.opt index 1364a0f82e5..329f71d92e8 100644 --- a/gcc/config/rs6000/476.opt +++ b/gcc/config/rs6000/476.opt @@ -21,4 +21,4 @@ mpreserve-link-stack Target Var(rs6000_link_stack) Init(-1) Save -Preserve the PowerPC 476's link stack by matching up a blr with the bcl/bl insns used for GOT accesses +Preserve the PowerPC 476's link stack by matching up a blr with the bcl/bl insns used for GOT accesses. diff --git a/gcc/config/rs6000/aix64.opt b/gcc/config/rs6000/aix64.opt index b6af1a80af7..c07bd54c6d9 100644 --- a/gcc/config/rs6000/aix64.opt +++ b/gcc/config/rs6000/aix64.opt @@ -21,15 +21,15 @@ maix64 Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags) -Compile for 64-bit pointers +Compile for 64-bit pointers. maix32 Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags) -Compile for 32-bit pointers +Compile for 32-bit pointers. mcmodel= Target RejectNegative Joined Enum(rs6000_cmodel) Var(rs6000_current_cmodel) -Select code model +Select code model. Enum Name(rs6000_cmodel) Type(enum rs6000_cmodel) @@ -46,7 +46,7 @@ Enum(rs6000_cmodel) String(large) Value(CMODEL_LARGE) mpe Target Report RejectNegative Var(internal_nothing_1) Save -Support message passing with the Parallel Environment +Support message passing with the Parallel Environment. posix Driver diff --git a/gcc/config/rs6000/darwin.opt b/gcc/config/rs6000/darwin.opt index d3cc790c969..9dbec3dd6a3 100644 --- a/gcc/config/rs6000/darwin.opt +++ b/gcc/config/rs6000/darwin.opt @@ -35,8 +35,8 @@ Driver RejectNegative Alias(mfix-and-continue) m64 Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) -Generate 64-bit code +Generate 64-bit code. m32 Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) -Generate 32-bit code +Generate 32-bit code. diff --git a/gcc/config/rs6000/linux64.opt b/gcc/config/rs6000/linux64.opt index 14167e954f5..47c049bbdb2 100644 --- a/gcc/config/rs6000/linux64.opt +++ b/gcc/config/rs6000/linux64.opt @@ -21,11 +21,11 @@ mprofile-kernel Target Report Var(profile_kernel) Save -Call mcount for profiling before a function prologue +Call mcount for profiling before a function prologue. mcmodel= Target RejectNegative Joined Enum(rs6000_cmodel) Var(rs6000_current_cmodel) -Select code model +Select code model. Enum Name(rs6000_cmodel) Type(enum rs6000_cmodel) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 6d11ff7dfdb..bb22d45fc26 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -106,91 +106,91 @@ Target RejectNegative Undocumented Ignore mpowerpc64 Target Report Mask(POWERPC64) Var(rs6000_isa_flags) -Use PowerPC-64 instruction set +Use PowerPC-64 instruction set. mpowerpc-gpopt Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) -Use PowerPC General Purpose group optional instructions +Use PowerPC General Purpose group optional instructions. mpowerpc-gfxopt Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) -Use PowerPC Graphics group optional instructions +Use PowerPC Graphics group optional instructions. mmfcrf Target Report Mask(MFCRF) Var(rs6000_isa_flags) -Use PowerPC V2.01 single field mfcr instruction +Use PowerPC V2.01 single field mfcr instruction. mpopcntb Target Report Mask(POPCNTB) Var(rs6000_isa_flags) -Use PowerPC V2.02 popcntb instruction +Use PowerPC V2.02 popcntb instruction. mfprnd Target Report Mask(FPRND) Var(rs6000_isa_flags) -Use PowerPC V2.02 floating point rounding instructions +Use PowerPC V2.02 floating point rounding instructions. mcmpb Target Report Mask(CMPB) Var(rs6000_isa_flags) -Use PowerPC V2.05 compare bytes instruction +Use PowerPC V2.05 compare bytes instruction. mmfpgpr Target Report Mask(MFPGPR) Var(rs6000_isa_flags) -Use extended PowerPC V2.05 move floating point to/from GPR instructions +Use extended PowerPC V2.05 move floating point to/from GPR instructions. maltivec Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) -Use AltiVec instructions +Use AltiVec instructions. maltivec=le Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save -Generate Altivec instructions using little-endian element order +Generate Altivec instructions using little-endian element order. maltivec=be Target Report RejectNegative Var(rs6000_altivec_element_order, 2) -Generate Altivec instructions using big-endian element order +Generate Altivec instructions using big-endian element order. mhard-dfp Target Report Mask(DFP) Var(rs6000_isa_flags) -Use decimal floating point instructions +Use decimal floating point instructions. mmulhw Target Report Mask(MULHW) Var(rs6000_isa_flags) -Use 4xx half-word multiply instructions +Use 4xx half-word multiply instructions. mdlmzb Target Report Mask(DLMZB) Var(rs6000_isa_flags) -Use 4xx string-search dlmzb instruction +Use 4xx string-search dlmzb instruction. mmultiple Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) -Generate load/store multiple instructions +Generate load/store multiple instructions. mstring Target Report Mask(STRING) Var(rs6000_isa_flags) -Generate string instructions for block moves +Generate string instructions for block moves. msoft-float Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) -Do not use hardware floating point +Do not use hardware floating point. mhard-float Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) -Use hardware floating point +Use hardware floating point. mpopcntd Target Report Mask(POPCNTD) Var(rs6000_isa_flags) -Use PowerPC V2.06 popcntd instruction +Use PowerPC V2.06 popcntd instruction. mfriz Target Report Var(TARGET_FRIZ) Init(-1) Save -Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions +Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions. mveclibabi= Target RejectNegative Joined Var(rs6000_veclibabi_name) -Vector library ABI to use +Vector library ABI to use. mvsx Target Report Mask(VSX) Var(rs6000_isa_flags) -Use vector/scalar (VSX) instructions +Use vector/scalar (VSX) instructions. mvsx-scalar-float Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1) @@ -237,42 +237,42 @@ Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) Save mno-update Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) -Do not generate load/store with update instructions +Do not generate load/store with update instructions. mupdate Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) -Generate load/store with update instructions +Generate load/store with update instructions. msingle-pic-base Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0) -Do not load the PIC register in function prologues +Do not load the PIC register in function prologues. mavoid-indexed-addresses Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save -Avoid generation of indexed load/store instructions when possible +Avoid generation of indexed load/store instructions when possible. mtls-markers Target Report Var(tls_markers) Init(1) Save -Mark __tls_get_addr calls with argument info +Mark __tls_get_addr calls with argument info. msched-epilog Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save msched-prolog Target Report Var(TARGET_SCHED_PROLOG) Save -Schedule the start and end of the procedure +Schedule the start and end of the procedure. maix-struct-return Target Report RejectNegative Var(aix_struct_return) Save -Return all structures in memory (AIX default) +Return all structures in memory (AIX default). msvr4-struct-return Target Report RejectNegative Var(aix_struct_return,0) Save -Return small structures in registers (SVR4 default) +Return small structures in registers (SVR4 default). mxl-compat Target Report Var(TARGET_XL_COMPAT) Save -Conform more closely to IBM XLC semantics +Conform more closely to IBM XLC semantics. mrecip Target Report @@ -288,19 +288,19 @@ Assume that the reciprocal estimate instructions provide more accuracy. mno-fp-in-toc Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save -Do not place floating point constants in TOC +Do not place floating point constants in TOC. mfp-in-toc Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save -Place floating point constants in TOC +Place floating point constants in TOC. mno-sum-in-toc Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save -Do not place symbol+offset constants in TOC +Do not place symbol+offset constants in TOC. msum-in-toc Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save -Place symbol+offset constants in TOC +Place symbol+offset constants in TOC. ; Output only one TOC entry per module. Normally linking fails if ; there are more than 16K unique variables/constants in an executable. With @@ -311,83 +311,83 @@ Place symbol+offset constants in TOC ; function, and one less allocable register. mminimal-toc Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) -Use only one TOC entry per procedure +Use only one TOC entry per procedure. mfull-toc Target Report -Put everything in the regular TOC +Put everything in the regular TOC. mvrsave Target Report Var(TARGET_ALTIVEC_VRSAVE) Save -Generate VRSAVE instructions when generating AltiVec code +Generate VRSAVE instructions when generating AltiVec code. mvrsave=no Target RejectNegative Alias(mvrsave) NegativeAlias -Deprecated option. Use -mno-vrsave instead +Deprecated option. Use -mno-vrsave instead. mvrsave=yes Target RejectNegative Alias(mvrsave) -Deprecated option. Use -mvrsave instead +Deprecated option. Use -mvrsave instead. mblock-move-inline-limit= Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save -Specify how many bytes should be moved inline before calling out to memcpy/memmove +Specify how many bytes should be moved inline before calling out to memcpy/memmove. misel Target Report Mask(ISEL) Var(rs6000_isa_flags) -Generate isel instructions +Generate isel instructions. misel=no Target RejectNegative Alias(misel) NegativeAlias -Deprecated option. Use -mno-isel instead +Deprecated option. Use -mno-isel instead. misel=yes Target RejectNegative Alias(misel) -Deprecated option. Use -misel instead +Deprecated option. Use -misel instead. mspe Target Var(rs6000_spe) Save -Generate SPE SIMD instructions on E500 +Generate SPE SIMD instructions on E500. mpaired Target Var(rs6000_paired_float) Save -Generate PPC750CL paired-single instructions +Generate PPC750CL paired-single instructions. mspe=no Target RejectNegative Alias(mspe) NegativeAlias -Deprecated option. Use -mno-spe instead +Deprecated option. Use -mno-spe instead. mspe=yes Target RejectNegative Alias(mspe) -Deprecated option. Use -mspe instead +Deprecated option. Use -mspe instead. mdebug= Target RejectNegative Joined --mdebug= Enable debug output +-mdebug= Enable debug output. mabi=altivec Target RejectNegative Var(rs6000_altivec_abi) Save -Use the AltiVec ABI extensions +Use the AltiVec ABI extensions. mabi=no-altivec Target RejectNegative Var(rs6000_altivec_abi, 0) -Do not use the AltiVec ABI extensions +Do not use the AltiVec ABI extensions. mabi=spe Target RejectNegative Var(rs6000_spe_abi) Save -Use the SPE ABI extensions +Use the SPE ABI extensions. mabi=no-spe Target RejectNegative Var(rs6000_spe_abi, 0) -Do not use the SPE ABI extensions +Do not use the SPE ABI extensions. mabi=elfv1 Target RejectNegative Var(rs6000_elf_abi, 1) Save -Use the ELFv1 ABI +Use the ELFv1 ABI. mabi=elfv2 Target RejectNegative Var(rs6000_elf_abi, 2) -Use the ELFv2 ABI +Use the ELFv2 ABI. ; These are here for testing during development only, do not document ; in the manual please. @@ -407,15 +407,15 @@ Target RejectNegative Undocumented Warn(using IBM extended precision long double mcpu= Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save --mcpu= Use features of and schedule code for given CPU +-mcpu= Use features of and schedule code for given CPU. mtune= Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save --mtune= Schedule code for given CPU +-mtune= Schedule code for given CPU. mtraceback= Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback) --mtraceback= Select full, part, or no traceback table +-mtraceback= Select full, part, or no traceback table. Enum Name(rs6000_traceback_type) Type(enum rs6000_traceback_type) @@ -431,23 +431,23 @@ Enum(rs6000_traceback_type) String(no) Value(traceback_none) mlongcall Target Report Var(rs6000_default_long_calls) Save -Avoid all range limits on call instructions +Avoid all range limits on call instructions. mgen-cell-microcode Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save -Generate Cell microcode +Generate Cell microcode. mwarn-cell-microcode Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save -Warn when a Cell microcoded instruction is emitted +Warn when a Cell microcoded instruction is emitted. mwarn-altivec-long Target Var(rs6000_warn_altivec_long) Init(1) Save -Warn about deprecated 'vector long ...' AltiVec type usage +Warn about deprecated 'vector long ...' AltiVec type usage. mfloat-gprs= Target RejectNegative Joined Enum(rs6000_float_gprs) Var(rs6000_float_gprs) Save --mfloat-gprs= Select GPR floating point method +-mfloat-gprs= Select GPR floating point method. Enum Name(rs6000_float_gprs) Type(unsigned char) @@ -467,23 +467,23 @@ Enum(rs6000_float_gprs) String(no) Value(0) mlong-double- Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save --mlong-double-<n> Specify size of long double (64 or 128 bits) +-mlong-double-<n> Specify size of long double (64 or 128 bits). mlra Target Report Var(rs6000_lra_flag) Init(0) Save -Use LRA instead of reload +Use LRA instead of reload. msched-costly-dep= Target RejectNegative Joined Var(rs6000_sched_costly_dep_str) -Determine which dependences between insns are considered costly +Determine which dependences between insns are considered costly. minsert-sched-nops= Target RejectNegative Joined Var(rs6000_sched_insert_nops_str) -Specify which post scheduling nop insertion scheme to apply +Specify which post scheduling nop insertion scheme to apply. malign- Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags) -Specify alignment of structure fields default/natural +Specify alignment of structure fields default/natural. Enum Name(rs6000_alignment_flags) Type(unsigned char) @@ -497,23 +497,23 @@ Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL) mprioritize-restricted-insns= Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save -Specify scheduling priority for dispatch slot restricted insns +Specify scheduling priority for dispatch slot restricted insns. msingle-float Target RejectNegative Var(rs6000_single_float) Save -Single-precision floating point unit +Single-precision floating point unit. mdouble-float Target RejectNegative Var(rs6000_double_float) Save -Double-precision floating point unit +Double-precision floating point unit. msimple-fpu Target RejectNegative Var(rs6000_simple_fpu) Save -Floating point unit does not support divide & sqrt +Floating point unit does not support divide & sqrt. mfpu= Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE) --mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu) +-mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu). Enum Name(fpu_type_t) Type(enum fpu_type_t) @@ -543,19 +543,19 @@ Use/do not use r11 to hold the static link in calls to functions via pointers. msave-toc-indirect Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags) -Control whether we save the TOC in the prologue for indirect calls or generate the save inline +Control whether we save the TOC in the prologue for indirect calls or generate the save inline. mvsx-timode Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags) -Allow 128-bit integers in VSX registers +Allow 128-bit integers in VSX registers. mpower8-fusion Target Report Mask(P8_FUSION) Var(rs6000_isa_flags) -Fuse certain integer operations together for better performance on power8 +Fuse certain integer operations together for better performance on power8. mpower8-fusion-sign Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) -Allow sign extension in fusion operations +Allow sign extension in fusion operations. mpower8-vector Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags) @@ -563,15 +563,15 @@ Use/do not use vector and scalar instructions added in ISA 2.07. mcrypto Target Report Mask(CRYPTO) Var(rs6000_isa_flags) -Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions +Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions. mdirect-move Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags) -Use ISA 2.07 direct move between GPR & VSX register instructions +Use ISA 2.07 direct move between GPR & VSX register instructions. mhtm Target Report Mask(HTM) Var(rs6000_isa_flags) -Use ISA 2.07 transactional memory (HTM) instructions +Use ISA 2.07 transactional memory (HTM) instructions. mquad-memory Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) @@ -587,15 +587,15 @@ Generate aggregate parameter passing code with at most 64-bit alignment. mupper-regs-df Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags) -Allow double variables in upper registers with -mcpu=power7 or -mvsx +Allow double variables in upper registers with -mcpu=power7 or -mvsx. mupper-regs-sf Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags) -Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector +Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector. mupper-regs Target Report Var(TARGET_UPPER_REGS) Init(-1) Save -Allow float/double variables in upper registers if cpu allows it +Allow float/double variables in upper registers if cpu allows it. moptimize-swaps Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save diff --git a/gcc/config/rs6000/sysv4.opt b/gcc/config/rs6000/sysv4.opt index 4514295fd54..addc9db0a4c 100644 --- a/gcc/config/rs6000/sysv4.opt +++ b/gcc/config/rs6000/sysv4.opt @@ -21,15 +21,15 @@ mcall- Target RejectNegative Joined Var(rs6000_abi_name) -Select ABI calling convention +Select ABI calling convention. msdata= Target RejectNegative Joined Var(rs6000_sdata_name) -Select method for sdata handling +Select method for sdata handling. mtls-size= Target RejectNegative Joined Var(rs6000_tls_size) Enum(rs6000_tls_size) -Specify bit size of immediate TLS offsets +Specify bit size of immediate TLS offsets. Enum Name(rs6000_tls_size) Type(int) @@ -45,113 +45,113 @@ Enum(rs6000_tls_size) String(64) Value(64) mbit-align Target Report Var(TARGET_NO_BITFIELD_TYPE) Save -Align to the base type of the bit-field +Align to the base type of the bit-field. mstrict-align Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags) -Align to the base type of the bit-field -Don't assume that unaligned accesses are handled by the system +Align to the base type of the bit-field. +Don't assume that unaligned accesses are handled by the system. mrelocatable Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags) -Produce code relocatable at runtime +Produce code relocatable at runtime. mrelocatable-lib Target -Produce code relocatable at runtime +Produce code relocatable at runtime. mlittle-endian Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) -Produce little endian code +Produce little endian code. mlittle Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) -Produce little endian code +Produce little endian code. mbig-endian Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) -Produce big endian code +Produce big endian code. mbig Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) -Produce big endian code +Produce big endian code. ;; FIXME: This does nothing. What should be done? mno-toc Target RejectNegative -no description yet +no description yet. mtoc Target RejectNegative -no description yet +no description yet. mprototype Target Var(target_prototype) Save -Assume all variable arg functions are prototyped +Assume all variable arg functions are prototyped. ;; FIXME: Does nothing. mno-traceback Target RejectNegative -no description yet +no description yet. meabi Target Report Mask(EABI) Var(rs6000_isa_flags) -Use EABI +Use EABI. mbit-word Target Report Var(TARGET_NO_BITFIELD_WORD) Save -Allow bit-fields to cross word boundaries +Allow bit-fields to cross word boundaries. mregnames Target Var(rs6000_regnames) Save -Use alternate register names +Use alternate register names. ;; This option does nothing and only exists because the compiler ;; driver passes all -m* options through. msdata Target -Use default method for sdata handling +Use default method for sdata handling. msim Target RejectNegative -Link with libsim.a, libc.a and sim-crt0.o +Link with libsim.a, libc.a and sim-crt0.o. mads Target RejectNegative -Link with libads.a, libc.a and crt0.o +Link with libads.a, libc.a and crt0.o. myellowknife Target RejectNegative -Link with libyk.a, libc.a and crt0.o +Link with libyk.a, libc.a and crt0.o. mmvme Target RejectNegative -Link with libmvme.a, libc.a and crt0.o +Link with libmvme.a, libc.a and crt0.o. memb Target RejectNegative -Set the PPC_EMB bit in the ELF flags header +Set the PPC_EMB bit in the ELF flags header. mshlib Target RejectNegative -no description yet +no description yet. m64 Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) -Generate 64-bit code +Generate 64-bit code. m32 Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) -Generate 32-bit code +Generate 32-bit code. mnewlib Target RejectNegative -no description yet +no description yet. msecure-plt Target Report RejectNegative Var(secure_plt, 1) Save -Generate code to use a non-exec PLT and GOT +Generate code to use a non-exec PLT and GOT. mbss-plt Target Report RejectNegative Var(secure_plt, 0) Save -Generate code for old exec BSS PLT +Generate code for old exec BSS PLT. diff --git a/gcc/config/s390/s390.opt b/gcc/config/s390/s390.opt index 7ef11d4f138..af82815fd82 100644 --- a/gcc/config/s390/s390.opt +++ b/gcc/config/s390/s390.opt @@ -36,15 +36,15 @@ HOST_WIDE_INT s390_warn_framesize = 0 m31 Target Report RejectNegative Negative(m64) InverseMask(64BIT) -31 bit ABI +31 bit ABI. m64 Target Report RejectNegative Negative(m31) Mask(64BIT) -64 bit ABI +64 bit ABI. march= Target RejectNegative Joined Enum(processor_type) Var(s390_arch) Init(PROCESSOR_max) -Generate code for given CPU +Generate code for given CPU. Enum Name(processor_type) Type(enum processor_type) @@ -84,23 +84,23 @@ Enum(processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly mbackchain Target Report Mask(BACKCHAIN) -Maintain backchain pointer +Maintain backchain pointer. mdebug Target Report Mask(DEBUG_ARG) -Additional debug prints +Additional debug prints. mesa Target Report RejectNegative Negative(mzarch) InverseMask(ZARCH) -ESA/390 architecture +ESA/390 architecture. mhard-dfp Target Report Mask(HARD_DFP) -Enable decimal floating point hardware support +Enable decimal floating point hardware support. mhard-float Target Report RejectNegative Negative(msoft-float) InverseMask(SOFT_FLOAT, HARD_FLOAT) -Enable hardware floating point +Enable hardware floating point. mhotpatch= Target RejectNegative Report Joined Var(s390_deferred_options) Defer @@ -114,47 +114,47 @@ size. Using 0 for both values disables hotpatching. mlong-double-128 Target Report RejectNegative Negative(mlong-double-64) Mask(LONG_DOUBLE_128) -Use 128-bit long double +Use 128-bit long double. mlong-double-64 Target Report RejectNegative Negative(mlong-double-128) InverseMask(LONG_DOUBLE_128) -Use 64-bit long double +Use 64-bit long double. mhtm Target Report Mask(OPT_HTM) -Use hardware transactional execution instructions +Use hardware transactional execution instructions. mvx Target Report Mask(OPT_VX) -Use hardware vector facility instructions and enable the vector ABI +Use hardware vector facility instructions and enable the vector ABI. mpacked-stack Target Report Mask(PACKED_STACK) -Use packed stack layout +Use packed stack layout. msmall-exec Target Report Mask(SMALL_EXEC) -Use bras for executable < 64k +Use bras for executable < 64k. msoft-float Target Report RejectNegative Negative(mhard-float) Mask(SOFT_FLOAT) -Disable hardware floating point +Disable hardware floating point. mstack-guard= Target RejectNegative Joined UInteger Var(s390_stack_guard) -Set the max. number of bytes which has to be left to stack size before a trap instruction is triggered +Set the max. number of bytes which has to be left to stack size before a trap instruction is triggered. mstack-size= Target RejectNegative Joined UInteger Var(s390_stack_size) -Emit extra code in the function prologue in order to trap if the stack size exceeds the given limit +Emit extra code in the function prologue in order to trap if the stack size exceeds the given limit. mtune= Target RejectNegative Joined Enum(processor_type) Var(s390_tune) Init(PROCESSOR_max) -Schedule code for given CPU +Schedule code for given CPU. mmvcle Target Report Mask(MVCLE) -mvcle use +mvcle use. mzvector Target Report Mask(ZVECTOR) @@ -163,15 +163,15 @@ vector macro and enable the Altivec-style builtins in vecintrin.h mwarn-dynamicstack Target RejectNegative Var(s390_warn_dynamicstack_p) -Warn if a function uses alloca or creates an array with dynamic size +Warn if a function uses alloca or creates an array with dynamic size. mwarn-framesize= Target RejectNegative Joined -Warn if a single function's framesize exceeds the given framesize +Warn if a single function's framesize exceeds the given framesize. mzarch Target Report RejectNegative Negative(mesa) Mask(ZARCH) -z/Architecture +z/Architecture. mbranch-cost= Target Report Joined RejectNegative UInteger Var(s390_branch_cost) Init(1) @@ -181,4 +181,4 @@ values are small, non-negative integers. The default branch cost is mlra Target Report Var(s390_lra_flag) Init(1) Save -Use LRA instead of reload +Use LRA instead of reload. diff --git a/gcc/config/s390/tpf.opt b/gcc/config/s390/tpf.opt index 504c84cdb3e..145f2f8df54 100644 --- a/gcc/config/s390/tpf.opt +++ b/gcc/config/s390/tpf.opt @@ -20,8 +20,8 @@ mtpf-trace Target Report Mask(TPF_PROFILING) -Enable TPF-OS tracing code +Enable TPF-OS tracing code. mmain Target Report -Specify main object for TPF-OS +Specify main object for TPF-OS. diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt index beb4bc8a017..5e3e88d27c5 100644 --- a/gcc/config/sh/sh.opt +++ b/gcc/config/sh/sh.opt @@ -45,82 +45,82 @@ Mask(SAVE_ALL_TARGET_REGS) m1 Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1) -Generate SH1 code +Generate SH1 code. m2 Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2) -Generate SH2 code +Generate SH2 code. m2a Target RejectNegative Condition(SUPPORT_SH2A) -Generate default double-precision SH2a-FPU code +Generate default double-precision SH2a-FPU code. m2a-nofpu Target RejectNegative Condition(SUPPORT_SH2A_NOFPU) -Generate SH2a FPU-less code +Generate SH2a FPU-less code. m2a-single Target RejectNegative Condition(SUPPORT_SH2A_SINGLE) -Generate default single-precision SH2a-FPU code +Generate default single-precision SH2a-FPU code. m2a-single-only Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY) -Generate only single-precision SH2a-FPU code +Generate only single-precision SH2a-FPU code. m2e Target RejectNegative Condition(SUPPORT_SH2E) -Generate SH2e code +Generate SH2e code. m3 Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) -Generate SH3 code +Generate SH3 code. m3e Target RejectNegative Condition(SUPPORT_SH3E) -Generate SH3e code +Generate SH3e code. m4 Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4) -Generate SH4 code +Generate SH4 code. m4-100 Target RejectNegative Condition(SUPPORT_SH4) -Generate SH4-100 code +Generate SH4-100 code. m4-200 Target RejectNegative Condition(SUPPORT_SH4) -Generate SH4-200 code +Generate SH4-200 code. ;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and ;; pipeline - irrespective of ABI. m4-300 Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300) -Generate SH4-300 code +Generate SH4-300 code. m4-nofpu Target RejectNegative Condition(SUPPORT_SH4_NOFPU) -Generate SH4 FPU-less code +Generate SH4 FPU-less code. m4-100-nofpu Target RejectNegative Condition(SUPPORT_SH4_NOFPU) -Generate SH4-100 FPU-less code +Generate SH4-100 FPU-less code. m4-200-nofpu Target RejectNegative Condition(SUPPORT_SH4_NOFPU) -Generate SH4-200 FPU-less code +Generate SH4-200 FPU-less code. m4-300-nofpu Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) -Generate SH4-300 FPU-less code +Generate SH4-300 FPU-less code. m4-340 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) -Generate code for SH4 340 series (MMU/FPU-less) +Generate code for SH4 340 series (MMU/FPU-less). ;; passes -isa=sh4-nommu-nofpu to the assembler. m4-400 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) -Generate code for SH4 400 series (MMU/FPU-less) +Generate code for SH4 400 series (MMU/FPU-less). ;; passes -isa=sh4-nommu-nofpu to the assembler. m4-500 @@ -130,83 +130,83 @@ Generate code for SH4 500 series (FPU-less). m4-single Target RejectNegative Condition(SUPPORT_SH4_SINGLE) -Generate default single-precision SH4 code +Generate default single-precision SH4 code. m4-100-single Target RejectNegative Condition(SUPPORT_SH4_SINGLE) -Generate default single-precision SH4-100 code +Generate default single-precision SH4-100 code. m4-200-single Target RejectNegative Condition(SUPPORT_SH4_SINGLE) -Generate default single-precision SH4-200 code +Generate default single-precision SH4-200 code. m4-300-single Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) -Generate default single-precision SH4-300 code +Generate default single-precision SH4-300 code. m4-single-only Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) -Generate only single-precision SH4 code +Generate only single-precision SH4 code. m4-100-single-only Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) -Generate only single-precision SH4-100 code +Generate only single-precision SH4-100 code. m4-200-single-only Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) -Generate only single-precision SH4-200 code +Generate only single-precision SH4-200 code. m4-300-single-only Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) -Generate only single-precision SH4-300 code +Generate only single-precision SH4-300 code. m4a Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A) -Generate SH4a code +Generate SH4a code. m4a-nofpu Target RejectNegative Condition(SUPPORT_SH4A_NOFPU) -Generate SH4a FPU-less code +Generate SH4a FPU-less code. m4a-single Target RejectNegative Condition(SUPPORT_SH4A_SINGLE) -Generate default single-precision SH4a code +Generate default single-precision SH4a code. m4a-single-only Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY) -Generate only single-precision SH4a code +Generate only single-precision SH4a code. m4al Target RejectNegative Condition(SUPPORT_SH4AL) -Generate SH4al-dsp code +Generate SH4al-dsp code. m5-32media Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) -Generate 32-bit SHmedia code +Generate 32-bit SHmedia code. m5-32media-nofpu Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) -Generate 32-bit FPU-less SHmedia code +Generate 32-bit FPU-less SHmedia code. m5-64media Target RejectNegative Condition(SUPPORT_SH5_64MEDIA) -Generate 64-bit SHmedia code +Generate 64-bit SHmedia code. m5-64media-nofpu Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU) -Generate 64-bit FPU-less SHmedia code +Generate 64-bit FPU-less SHmedia code. m5-compact Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) -Generate SHcompact code +Generate SHcompact code. m5-compact-nofpu Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) -Generate FPU-less SHcompact code +Generate FPU-less SHcompact code. maccumulate-outgoing-args Target Report Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1) -Reserve space for outgoing arguments in the function prologue +Reserve space for outgoing arguments in the function prologue. madjust-unroll Target Ignore @@ -214,27 +214,27 @@ Does nothing. Preserved for backward compatibility. mb Target Report RejectNegative InverseMask(LITTLE_ENDIAN) -Generate code in big endian mode +Generate code in big endian mode. mbigtable Target Report RejectNegative Mask(BIGTABLE) -Generate 32-bit offsets in switch tables +Generate 32-bit offsets in switch tables. mbitops Target Report RejectNegative Mask(BITOPS) -Generate bit instructions +Generate bit instructions. mbranch-cost= Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1) -Cost to assume for a branch insn +Cost to assume for a branch insn. mzdcbranch Target Report Var(TARGET_ZDCBRANCH) -Assume that zero displacement conditional branches are fast +Assume that zero displacement conditional branches are fast. mcbranchdi Target Undocumented Var(TARGET_CBRANCHDI4) Warn(%qs is deprecated and has no effect) -Enable cbranchdi4 pattern +Enable cbranchdi4 pattern. mcmpeqdi Target Undocumented Var(TARGET_CMPEQDI_T) Warn(%qs is deprecated and has no effect) @@ -246,19 +246,19 @@ Force the usage of delay slots for conditional branches. mcut2-workaround Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND) -Enable SH5 cut2 workaround +Enable SH5 cut2 workaround. mdalign Target Report RejectNegative Mask(ALIGN_DOUBLE) -Align doubles at 64-bit boundaries +Align doubles at 64-bit boundaries. mdiv= Target RejectNegative Joined Var(sh_div_str) Init("") -Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table +Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table. mdivsi3_libfunc= Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("") -Specify name for 32 bit signed division function +Specify name for 32 bit signed division function. mfmovd Target RejectNegative Mask(FMOVD) @@ -266,53 +266,53 @@ Enable the use of 64-bit floating point registers in fmov instructions. See -md mfixed-range= Target RejectNegative Joined Var(sh_fixed_range_str) -Specify range of registers to make fixed +Specify range of registers to make fixed. mgettrcost= Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1) -Cost to assume for gettr insn +Cost to assume for gettr insn. mhitachi Target Report RejectNegative Mask(HITACHI) -Follow Renesas (formerly Hitachi) / SuperH calling conventions +Follow Renesas (formerly Hitachi) / SuperH calling conventions. mieee Target Var(TARGET_IEEE) -Increase the IEEE compliance for floating-point comparisons +Increase the IEEE compliance for floating-point comparisons. mindexed-addressing Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA) -Enable the use of the indexed addressing mode for SHmedia32/SHcompact +Enable the use of the indexed addressing mode for SHmedia32/SHcompact. minline-ic_invalidate Target Report Var(TARGET_INLINE_IC_INVALIDATE) -inline code to invalidate instruction cache entries after setting up nested function trampolines +inline code to invalidate instruction cache entries after setting up nested function trampolines. minvalid-symbols Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5) -Assume symbols might be invalid +Assume symbols might be invalid. misize Target Report RejectNegative Mask(DUMPISIZE) -Annotate assembler instructions with estimated addresses +Annotate assembler instructions with estimated addresses. ml Target Report RejectNegative Mask(LITTLE_ENDIAN) -Generate code in little endian mode +Generate code in little endian mode. mnomacsave Target Report RejectNegative Mask(NOMACSAVE) -Mark MAC register as call-clobbered +Mark MAC register as call-clobbered. ;; ??? This option is not useful, but is retained in case there are people ;; who are still relying on it. It may be deleted in the future. mpadstruct Target Report RejectNegative Mask(PADSTRUCT) -Make structs a multiple of 4 bytes (warning: ABI altered) +Make structs a multiple of 4 bytes (warning: ABI altered). mprefergot Target Report RejectNegative Mask(PREFERGOT) -Emit function-calls using global offset table when generating PIC +Emit function-calls using global offset table when generating PIC. mpt-fixed Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5) @@ -320,31 +320,31 @@ Assume pt* instructions won't trap mrelax Target Report RejectNegative Mask(RELAX) -Shorten address references during linking +Shorten address references during linking. mrenesas Target Mask(HITACHI) -Follow Renesas (formerly Hitachi) / SuperH calling conventions +Follow Renesas (formerly Hitachi) / SuperH calling conventions. msoft-atomic Target Undocumented Alias(matomic-model=, soft-gusa, none) -Deprecated. Use -matomic= instead to select the atomic model +Deprecated. Use -matomic= instead to select the atomic model. matomic-model= Target Report RejectNegative Joined Var(sh_atomic_model_str) -Specify the model for atomic operations +Specify the model for atomic operations. mtas Target Report RejectNegative Var(TARGET_ENABLE_TAS) -Use tas.b instruction for __atomic_test_and_set +Use tas.b instruction for __atomic_test_and_set. mspace Target RejectNegative Alias(Os) -Deprecated. Use -Os instead +Deprecated. Use -Os instead. multcost= Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1) -Cost to assume for a multiply insn +Cost to assume for a multiply insn. musermode Target Var(TARGET_USERMODE) @@ -358,12 +358,12 @@ Pretend a branch-around-a-move is a conditional move. mfsca Target Var(TARGET_FSCA) -Enable the use of the fsca instruction +Enable the use of the fsca instruction. mfsrra Target Var(TARGET_FSRRA) -Enable the use of the fsrra instruction +Enable the use of the fsrra instruction. mlra Target Report Var(sh_lra_flag) Init(0) Save -Use LRA instead of reload (transitional) +Use LRA instead of reload (transitional). diff --git a/gcc/config/sol2.opt b/gcc/config/sol2.opt index ed2edea0090..f2ae2cab5d4 100644 --- a/gcc/config/sol2.opt +++ b/gcc/config/sol2.opt @@ -29,11 +29,11 @@ Driver Joined mclear-hwcap Target Report -Clear hardware capabilities when linking +Clear hardware capabilities when linking. mimpure-text Target Report -Pass -z text to linker +Pass -z text to linker. pthread Driver diff --git a/gcc/config/sparc/long-double-switch.opt b/gcc/config/sparc/long-double-switch.opt index fede08b928a..ca7cb7a48ae 100644 --- a/gcc/config/sparc/long-double-switch.opt +++ b/gcc/config/sparc/long-double-switch.opt @@ -20,8 +20,8 @@ mlong-double-128 Target Report RejectNegative Mask(LONG_DOUBLE_128) -Use 128-bit long double +Use 128-bit long double. mlong-double-64 Target Report RejectNegative InverseMask(LONG_DOUBLE_128) -Use 64-bit long double +Use 64-bit long double. diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt index 85bf0bdb493..249d33bc209 100644 --- a/gcc/config/sparc/sparc.opt +++ b/gcc/config/sparc/sparc.opt @@ -27,103 +27,103 @@ unsigned int sparc_debug mfpu Target Report Mask(FPU) -Use hardware FP +Use hardware FP. mhard-float Target RejectNegative Mask(FPU) -Use hardware FP +Use hardware FP. msoft-float Target RejectNegative InverseMask(FPU) -Do not use hardware FP +Do not use hardware FP. mflat Target Report Mask(FLAT) -Use flat register window model +Use flat register window model. munaligned-doubles Target Report Mask(UNALIGNED_DOUBLES) -Assume possible double misalignment +Assume possible double misalignment. mapp-regs Target Report Mask(APP_REGS) -Use ABI reserved registers +Use ABI reserved registers. mhard-quad-float Target Report RejectNegative Mask(HARD_QUAD) -Use hardware quad FP instructions +Use hardware quad FP instructions. msoft-quad-float Target Report RejectNegative InverseMask(HARD_QUAD) -Do not use hardware quad fp instructions +Do not use hardware quad fp instructions. mv8plus Target Report Mask(V8PLUS) -Compile for V8+ ABI +Compile for V8+ ABI. mvis Target Report Mask(VIS) -Use UltraSPARC Visual Instruction Set version 1.0 extensions +Use UltraSPARC Visual Instruction Set version 1.0 extensions. mvis2 Target Report Mask(VIS2) -Use UltraSPARC Visual Instruction Set version 2.0 extensions +Use UltraSPARC Visual Instruction Set version 2.0 extensions. mvis3 Target Report Mask(VIS3) -Use UltraSPARC Visual Instruction Set version 3.0 extensions +Use UltraSPARC Visual Instruction Set version 3.0 extensions. mcbcond Target Report Mask(CBCOND) -Use UltraSPARC Compare-and-Branch extensions +Use UltraSPARC Compare-and-Branch extensions. mfmaf Target Report Mask(FMAF) -Use UltraSPARC Fused Multiply-Add extensions +Use UltraSPARC Fused Multiply-Add extensions. mpopc Target Report Mask(POPC) -Use UltraSPARC Population-Count instruction +Use UltraSPARC Population-Count instruction. mptr64 Target Report RejectNegative Mask(PTR64) -Pointers are 64-bit +Pointers are 64-bit. mptr32 Target Report RejectNegative InverseMask(PTR64) -Pointers are 32-bit +Pointers are 32-bit. m64 Target Report RejectNegative Mask(64BIT) -Use 64-bit ABI +Use 64-bit ABI. m32 Target Report RejectNegative InverseMask(64BIT) -Use 32-bit ABI +Use 32-bit ABI. mstack-bias Target Report Mask(STACK_BIAS) -Use stack bias +Use stack bias. mfaster-structs Target Report Mask(FASTER_STRUCTS) -Use structs on stronger alignment for double-word copies +Use structs on stronger alignment for double-word copies. mrelax Target -Optimize tail call instructions in assembler and linker +Optimize tail call instructions in assembler and linker. muser-mode Target Report InverseMask(SV_MODE) -Do not generate code that can only run in supervisor mode (default) +Do not generate code that can only run in supervisor mode (default). mcpu= Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7) -Use features of and schedule code for given CPU +Use features of and schedule code for given CPU. mtune= Target RejectNegative Joined Var(sparc_cpu) Enum(sparc_processor_type) Init(PROCESSOR_V7) -Schedule code for given CPU +Schedule code for given CPU. Enum Name(sparc_processor_type) Type(enum processor_type) @@ -196,11 +196,11 @@ Enum(sparc_processor_type) String(niagara4) Value(PROCESSOR_NIAGARA4) mcmodel= Target RejectNegative Joined Var(sparc_cmodel_string) -Use given SPARC-V9 code model +Use given SPARC-V9 code model. mdebug= Target RejectNegative Joined Var(sparc_debug_string) -Enable debug output +Enable debug output. mstd-struct-return Target Report RejectNegative Var(sparc_std_struct_return) @@ -213,7 +213,7 @@ Enable workaround for single erratum of AT697F processor mfix-ut699 Target Report RejectNegative Var(sparc_fix_ut699) -Enable workarounds for the errata of the UT699 processor +Enable workarounds for the errata of the UT699 processor. Mask(LONG_DOUBLE_128) ;; Use 128-bit long double diff --git a/gcc/config/spu/spu.opt b/gcc/config/spu/spu.opt index f57ae3818d3..8f0abb7d69b 100644 --- a/gcc/config/spu/spu.opt +++ b/gcc/config/spu/spu.opt @@ -17,89 +17,89 @@ mwarn-reloc Target Report Mask(WARN_RELOC) -Emit warnings when run-time relocations are generated +Emit warnings when run-time relocations are generated. merror-reloc Target Report Mask(ERROR_RELOC) -Emit errors when run-time relocations are generated +Emit errors when run-time relocations are generated. mbranch-cost= Target RejectNegative Joined UInteger Var(spu_branch_cost) Init(20) -Specify cost of branches (Default 20) +Specify cost of branches (Default 20). msafe-dma Target Report RejectNegative Mask(SAFE_DMA) -Make sure loads and stores are not moved past DMA instructions +Make sure loads and stores are not moved past DMA instructions. munsafe-dma Target Report RejectNegative InverseMask(SAFE_DMA) -volatile must be specified on any memory that is effected by DMA +volatile must be specified on any memory that is effected by DMA. mdual-nops Target Report Var(spu_dual_nops,10) Init(10) -Insert nops when it might improve performance by allowing dual issue (default) +Insert nops when it might improve performance by allowing dual issue (default). mdual-nops= Target RejectNegative Joined UInteger Var(spu_dual_nops) -Insert nops when it might improve performance by allowing dual issue (default) +Insert nops when it might improve performance by allowing dual issue (default). mstdmain Target Report Mask(STD_MAIN) -Use standard main function as entry for startup +Use standard main function as entry for startup. mbranch-hints Target Report Mask(BRANCH_HINTS) -Generate branch hints for branches +Generate branch hints for branches. mhint-max-nops= Target RejectNegative Joined UInteger Var(spu_max_nops) Init(2) -Maximum number of nops to insert for a hint (Default 2) +Maximum number of nops to insert for a hint (Default 2). mhint-max-distance= Target RejectNegative Joined Var(spu_max_distance_str) -Approximate maximum number of instructions to allow between a hint and its branch [125] +Approximate maximum number of instructions to allow between a hint and its branch [125]. msmall-mem Target Report RejectNegative InverseMask(LARGE_MEM) -Generate code for 18 bit addressing +Generate code for 18 bit addressing. mlarge-mem Target Report RejectNegative Mask(LARGE_MEM) -Generate code for 32 bit addressing +Generate code for 32 bit addressing. mfixed-range= Target RejectNegative Joined Var(spu_fixed_range_string) -Specify range of registers to make fixed +Specify range of registers to make fixed. msafe-hints Target Report Mask(SAFE_HINTS) -Insert hbrp instructions after hinted branch targets to avoid the SPU hang issue +Insert hbrp instructions after hinted branch targets to avoid the SPU hang issue. march= Target RejectNegative Joined Var(spu_arch_string) -Generate code for given CPU +Generate code for given CPU. mtune= Target RejectNegative Joined Var(spu_tune_string) -Schedule code for given CPU +Schedule code for given CPU. mea32 Target Report RejectNegative Var(spu_ea_model,32) Init(32) -Access variables in 32-bit PPU objects (default) +Access variables in 32-bit PPU objects (default). mea64 Target Report RejectNegative Var(spu_ea_model,64) -Access variables in 64-bit PPU objects +Access variables in 64-bit PPU objects. maddress-space-conversion Target Report Mask(ADDRESS_SPACE_CONVERSION) -Allow conversions between __ea and generic pointers (default) +Allow conversions between __ea and generic pointers (default). mcache-size= Target Report RejectNegative Joined UInteger -Size (in KB) of software data cache +Size (in KB) of software data cache. matomic-updates Target Report -Atomically write back software data cache lines (default) +Atomically write back software data cache lines (default). diff --git a/gcc/config/stormy16/stormy16.opt b/gcc/config/stormy16/stormy16.opt index db511c4433d..5a457dc6c9e 100644 --- a/gcc/config/stormy16/stormy16.opt +++ b/gcc/config/stormy16/stormy16.opt @@ -21,4 +21,4 @@ ; Not used by the compiler msim Target RejectNegative -Provide libraries for the simulator +Provide libraries for the simulator. diff --git a/gcc/config/tilegx/tilegx.opt b/gcc/config/tilegx/tilegx.opt index 5881c6dcb10..89f7bcfaeb4 100644 --- a/gcc/config/tilegx/tilegx.opt +++ b/gcc/config/tilegx/tilegx.opt @@ -23,7 +23,7 @@ config/tilegx/tilegx-opts.h mcpu= Target RejectNegative Joined Enum(tilegx_cpu) Var(tilegx_cpu) Init(0) --mcpu=CPU Use features of and schedule code for given CPU +-mcpu=CPU Use features of and schedule code for given CPU. Enum Name(tilegx_cpu) Type(int) @@ -50,7 +50,7 @@ Use little-endian byte order. mcmodel= Target RejectNegative Joined Enum(cmodel) Var(tilegx_cmodel) Init(CM_SMALL) -Use given TILE-Gx code model +Use given TILE-Gx code model. Enum Name(cmodel) Type(enum cmodel) diff --git a/gcc/config/tilepro/tilepro.opt b/gcc/config/tilepro/tilepro.opt index 583d18fa227..07cef5e2b53 100644 --- a/gcc/config/tilepro/tilepro.opt +++ b/gcc/config/tilepro/tilepro.opt @@ -25,7 +25,7 @@ behavior and thus the flag is ignored. mcpu= Target RejectNegative Joined Enum(tilepro_cpu) Var(tilepro_cpu) Init(0) --mcpu=CPU Use features of and schedule code for given CPU +-mcpu=CPU Use features of and schedule code for given CPU. Enum Name(tilepro_cpu) Type(int) diff --git a/gcc/config/v850/v850.opt b/gcc/config/v850/v850.opt index c1ded1f95a3..d33b87b9d51 100644 --- a/gcc/config/v850/v850.opt +++ b/gcc/config/v850/v850.opt @@ -26,134 +26,134 @@ int small_memory_max[(int)SMALL_MEMORY_max] = { 0, 0, 0 } mapp-regs Target Report Mask(APP_REGS) -Use registers r2 and r5 +Use registers r2 and r5. mbig-switch Target Report Mask(BIG_SWITCH) -Use 4 byte entries in switch tables +Use 4 byte entries in switch tables. mdebug Target Report Mask(DEBUG) -Enable backend debugging +Enable backend debugging. mdisable-callt Target Report Mask(DISABLE_CALLT) -Do not use the callt instruction (default) +Do not use the callt instruction (default). mep Target Report Mask(EP) -Reuse r30 on a per function basis +Reuse r30 on a per function basis. mghs Target RejectNegative InverseMask(GCC_ABI) MaskExists mlong-calls Target Report Mask(LONG_CALLS) -Prohibit PC relative function calls +Prohibit PC relative function calls. mprolog-function Target Report Mask(PROLOG_FUNCTION) -Use stubs for function prologues +Use stubs for function prologues. msda= Target RejectNegative Joined UInteger -Set the max size of data eligible for the SDA area +Set the max size of data eligible for the SDA area. msda- Target RejectNegative Joined Undocumented Alias(msda=) msmall-sld Target Report Mask(SMALL_SLD) -Enable the use of the short load instructions +Enable the use of the short load instructions. mspace Target RejectNegative -Same as: -mep -mprolog-function +Same as: -mep -mprolog-function. mtda= Target RejectNegative Joined UInteger -Set the max size of data eligible for the TDA area +Set the max size of data eligible for the TDA area. mtda- Target RejectNegative Joined Undocumented Alias(mtda=) mno-strict-align Target Report Mask(NO_STRICT_ALIGN) -Do not enforce strict alignment +Do not enforce strict alignment. mjump-tables-in-data-section Target Report Mask(JUMP_TABLES_IN_DATA_SECTION) -Put jump tables for switch statements into the .data section rather than the .code section +Put jump tables for switch statements into the .data section rather than the .code section. mUS-bit-set Target Report Mask(US_BIT_SET) mv850 Target Report RejectNegative Mask(V850) -Compile for the v850 processor +Compile for the v850 processor. mv850e Target Report RejectNegative Mask(V850E) -Compile for the v850e processor +Compile for the v850e processor. mv850e1 Target RejectNegative Mask(V850E1) -Compile for the v850e1 processor +Compile for the v850e1 processor. mv850es Target RejectNegative Mask(V850E1) -Compile for the v850es variant of the v850e1 +Compile for the v850es variant of the v850e1. mv850e2 Target Report RejectNegative Mask(V850E2) -Compile for the v850e2 processor +Compile for the v850e2 processor. mv850e2v3 Target Report RejectNegative Mask(V850E2V3) -Compile for the v850e2v3 processor +Compile for the v850e2v3 processor. mv850e3v5 Target Report RejectNegative Mask(V850E3V5) -Compile for the v850e3v5 processor +Compile for the v850e3v5 processor. mv850e2v4 Target RejectNegative Mask(V850E3V5) MaskExists mloop Target Report Mask(LOOP) -Enable v850e3v5 loop instructions +Enable v850e3v5 loop instructions. mzda= Target RejectNegative Joined UInteger -Set the max size of data eligible for the ZDA area +Set the max size of data eligible for the ZDA area. mzda- Target RejectNegative Joined Undocumented Alias(mzda=) mrelax Target Report Mask(RELAX) -Enable relaxing in the assembler +Enable relaxing in the assembler. mlong-jumps Target Report Mask(BIG_SWITCH) MaskExists -Prohibit PC relative jumps +Prohibit PC relative jumps. msoft-float Target Report RejectNegative Mask(SOFT_FLOAT) -Inhibit the use of hardware floating point instructions +Inhibit the use of hardware floating point instructions. mhard-float Target Report RejectNegative InverseMask(SOFT_FLOAT) MaskExists -Allow the use of hardware floating point instructions for V850E2V3 and up +Allow the use of hardware floating point instructions for V850E2V3 and up. mrh850-abi Target RejectNegative Report InverseMask(GCC_ABI) MaskExists -Enable support for the RH850 ABI. This is the default +Enable support for the RH850 ABI. This is the default. mgcc-abi Target RejectNegative Report Mask(GCC_ABI) -Enable support for the old GCC ABI +Enable support for the old GCC ABI. m8byte-align Target Report Mask(8BYTE_ALIGN) -Support alignments of up to 64-bits +Support alignments of up to 64-bits. diff --git a/gcc/config/vax/vax.opt b/gcc/config/vax/vax.opt index 5779c8b3d85..4dfb28cc1b0 100644 --- a/gcc/config/vax/vax.opt +++ b/gcc/config/vax/vax.opt @@ -20,32 +20,32 @@ md Target RejectNegative InverseMask(G_FLOAT) -Target DFLOAT double precision code +Target DFLOAT double precision code. md-float Target RejectNegative InverseMask(G_FLOAT) -Target DFLOAT double precision code +Target DFLOAT double precision code. mg Target RejectNegative Mask(G_FLOAT) -Generate GFLOAT double precision code +Generate GFLOAT double precision code. mg-float Target RejectNegative Mask(G_FLOAT) -Generate GFLOAT double precision code +Generate GFLOAT double precision code. mgnu Target RejectNegative InverseMask(UNIX_ASM) -Generate code for GNU assembler (gas) +Generate code for GNU assembler (gas). munix Target RejectNegative Mask(UNIX_ASM) -Generate code for UNIX assembler +Generate code for UNIX assembler. mvaxc-alignment Target RejectNegative Mask(VAXC_ALIGNMENT) -Use VAXC structure conventions +Use VAXC structure conventions. mqmath Target Mask(QMATH) -Use new adddi3/subdi3 patterns +Use new adddi3/subdi3 patterns. diff --git a/gcc/config/visium/visium.opt b/gcc/config/visium/visium.opt index 74fbb32db0b..cb42294c4a3 100644 --- a/gcc/config/visium/visium.opt +++ b/gcc/config/visium/visium.opt @@ -22,31 +22,31 @@ config/visium/visium-opts.h mdebug Target RejectNegative -Link with libc.a and libdebug.a +Link with libc.a and libdebug.a. msim Target RejectNegative -Link with libc.a and libsim.a +Link with libc.a and libsim.a. mfpu Target Report Mask(FPU) -Use hardware FP (default) +Use hardware FP (default). mhard-float Target RejectNegative Mask(FPU) MaskExists -Use hardware FP +Use hardware FP. msoft-float Target RejectNegative InverseMask(FPU) -Do not use hardware FP +Do not use hardware FP. mcpu= Target RejectNegative Joined Var(visium_cpu_and_features) Enum(visium_processor_type) Init(PROCESSOR_GR5) -Use features of and schedule code for given CPU +Use features of and schedule code for given CPU. mtune= Target RejectNegative Joined Var(visium_cpu) Enum(visium_processor_type) Init(PROCESSOR_GR5) -Schedule code for given CPU +Schedule code for given CPU. Enum Name(visium_processor_type) Type(enum processor_type) @@ -62,11 +62,11 @@ Enum(visium_processor_type) String(gr6) Value(PROCESSOR_GR6) msv-mode Target RejectNegative Report Mask(SV_MODE) -Generate code for the supervisor mode (default) +Generate code for the supervisor mode (default). muser-mode Target RejectNegative Report InverseMask(SV_MODE) -Generate code for the user mode +Generate code for the user mode. menable-trampolines Target RejectNegative diff --git a/gcc/config/vms/vms.opt b/gcc/config/vms/vms.opt index 6e36a65d811..4cbae2738c3 100644 --- a/gcc/config/vms/vms.opt +++ b/gcc/config/vms/vms.opt @@ -24,19 +24,19 @@ Target RejectNegative mmalloc64 Target Report Var(flag_vms_malloc64) Init(1) -Malloc data into P2 space +Malloc data into P2 space. mdebug-main= Target RejectNegative Joined Var(vms_debug_main) -Set name of main routine for the debugger +Set name of main routine for the debugger. mvms-return-codes Target Report Var(flag_vms_return_codes) -Use VMS exit codes instead of posix ones +Use VMS exit codes instead of posix ones. mpointer-size= Target Joined Report RejectNegative Enum(vms_pointer_size) Var(flag_vms_pointer_size) Init(VMS_POINTER_SIZE_NONE) --mpointer-size=[no,32,short,64,long] Set the default pointer size +-mpointer-size=[no,32,short,64,long] Set the default pointer size. Enum Name(vms_pointer_size) Type(enum vms_pointer_size) UnknownError(unknown pointer size model %qs) diff --git a/gcc/config/vxworks.opt b/gcc/config/vxworks.opt index 623c07d5983..8ddefe0ad30 100644 --- a/gcc/config/vxworks.opt +++ b/gcc/config/vxworks.opt @@ -33,14 +33,14 @@ Driver Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL) mrtp Target Report RejectNegative Mask(VXWORKS_RTP) Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL) -Assume the VxWorks RTP environment +Assume the VxWorks RTP environment. ; VxWorks AE has two modes: kernel mode and vThreads mode. In ; general, back ends do not actually need to know which mode they're ; in, so we do not have to set any flags. mvthreads Target RejectNegative Condition(VXWORKS_KIND == VXWORKS_KIND_AE) -Assume the VxWorks vThreads environment +Assume the VxWorks vThreads environment. non-static Driver Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL) diff --git a/gcc/config/xtensa/xtensa.opt b/gcc/config/xtensa/xtensa.opt index 21c6e962abb..df1d3380043 100644 --- a/gcc/config/xtensa/xtensa.opt +++ b/gcc/config/xtensa/xtensa.opt @@ -20,28 +20,28 @@ mconst16 Target Report Mask(CONST16) -Use CONST16 instruction to load constants +Use CONST16 instruction to load constants. mforce-no-pic Target Report Mask(FORCE_NO_PIC) -Disable position-independent code (PIC) for use in OS kernel code +Disable position-independent code (PIC) for use in OS kernel code. mlongcalls Target -Use indirect CALLXn instructions for large programs +Use indirect CALLXn instructions for large programs. mtarget-align Target -Automatically align branch targets to reduce branch penalties +Automatically align branch targets to reduce branch penalties. mtext-section-literals Target -Intersperse literal pools with code in the text section +Intersperse literal pools with code in the text section. mauto-litpools Target Report Mask(AUTO_LITPOOLS) -Relax literals in assembler and place them automatically in the text section +Relax literals in assembler and place them automatically in the text section. mserialize-volatile Target Report Mask(SERIALIZE_VOLATILE) --mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions +-mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions. |