Support clwb x86 instruction.

gcc/
	* common/config/i386/i386-common.c (OPTION_MASK_ISA_CLWB_UNSET,
	OPTION_MASK_ISA_CLWB_SET): New.
	(ix86_handle_option): Handle OPT_mclwb.
	* config.gcc: Add clwbintrin.h.
	* config/i386/clwbintrin.h: New file.
	* config/i386/cpuid.h (bit_CLWB): Define.
	* config/i386/driver-i386.c (host_detect_local_cpu): Detect clwb. 
	* config/i386/i386-c.c (ix86_target_macros_internal): Define
	__CLWB__.
	* config/i386/i386.c (ix86_target_string): Add -mclwb.
	(PTA_CLWB): Define.
	(ix86_option_override_internal): Handle new option.
	(ix86_valid_target_attribute_inner_p): Add clwb.
	(ix86_builtins): Add IX86_BUILTIN_CLWB.
	(ix86_init_mmx_sse_builtins): Add __builtin_ia32_clwb.
	(ix86_expand_builtin): Handle IX86_BUILTIN_CLWB.
	* config/i386/i386.h (TARGET_CLWB, TARGET_CLWB_P): Define.
	* config/i386/i386.md (unspecv): Add UNSPECV_CLWB.
	(clwb): New instruction.
	* config/i386/i386.opt: Add mclwb.
	* config/i386/x86intrin.h: Include clwbintrin.h.

gcc/testsuite/

	* g++.dg/other/i386-2.C: Add -mclwb.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.target/i386/clwb-1.c: New test.
	* gcc.target/i386/sse-12.c: Add new options.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-14.c: Ditto.
	* gcc.target/i386/sse-22.c: Ditto.
	* gcc.target/i386/sse-23.c: Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217933 138bc75d-0d04-0410-961f-82ee72b054a4

9 files changed, 99 insertions, 2 deletions

diff --git a/gcc/config/i386/clwbintrin.h b/gcc/config/i386/clwbintrin.h
new file mode 100644
index 00000000000..9020c955213
--- /dev/null
+++ b/gcc/config/i386/clwbintrin.h
@@ -0,0 +1,49 @@
+/* Copyright (C) 2013 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#if !defined _X86INTRIN_H_INCLUDED
+# error "Never use <clwbintrin.h> directly; include <x86intrin.h> instead."
+#endif
+
+#ifndef _CLWBINTRIN_H_INCLUDED
+#define _CLWBINTRIN_H_INCLUDED
+
+#ifndef __CLWB__
+#pragma GCC push_options
+#pragma GCC target("clwb")
+#define __DISABLE_CLWB__
+#endif /* __CLWB__ */
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_clwb (void *__A)
+{
+  __builtin_ia32_clwb (__A);
+}
+
+#ifdef __DISABLE_CLWB__
+#undef __DISABLE_CLWB__
+#pragma GCC pop_options
+#endif /* __DISABLE_CLWB__ */
+
+#endif /* _CLWBINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 0efb1a4a75a..6ee928bc746 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -78,6 +78,7 @@
 #define bit_ADX	(1 << 19)
 #define bit_AVX512IFMA	(1 << 21)
 #define bit_CLFLUSHOPT	(1 << 23)
+#define bit_CLWB	(1 << 24)
 #define bit_AVX512PF	(1 << 26)
 #define bit_AVX512ER	(1 << 27)
 #define bit_AVX512CD	(1 << 28)
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 72dfd04593c..c7acfbac3ee 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -412,7 +412,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
   unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
   unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
   unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
-  unsigned int has_avx512vbmi = 0, has_avx512ifma = 0;
+  unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
 
   bool arch;
 
@@ -491,6 +491,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       has_avx512cd = ebx & bit_AVX512CD;
       has_sha = ebx & bit_SHA;
       has_clflushopt = ebx & bit_CLFLUSHOPT;
+      has_clwb = ebx & bit_CLWB;
       has_avx512dq = ebx & bit_AVX512DQ;
       has_avx512bw = ebx & bit_AVX512BW;
       has_avx512vl = ebx & bit_AVX512VL;
@@ -930,6 +931,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
       const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
       const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
+      const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
 
       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
 			sse4a, cx16, sahf, movbe, aes, sha, pclmul,
@@ -939,7 +941,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 			fxsr, xsave, xsaveopt, avx512f, avx512er,
 			avx512cd, avx512pf, prefetchwt1, clflushopt,
 			xsavec, xsaves, avx512dq, avx512bw, avx512vl,
-			avx512ifma, avx512vbmi, NULL);
+			avx512ifma, avx512vbmi, clwb, NULL);
     }
 
 done:
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 798eaa6ba30..9742536083f 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -411,6 +411,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     def_or_undef (parse_in, "__XSAVES__");
   if (isa_flag & OPTION_MASK_ISA_MPX)
     def_or_undef (parse_in, "__MPX__");
+  if (isa_flag & OPTION_MASK_ISA_CLWB)
+    def_or_undef (parse_in, "__CLWB__");
 }
 
 
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 95af5fcb952..960e4406366 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2657,6 +2657,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
     { "-mxsavec",	OPTION_MASK_ISA_XSAVEC },
     { "-mxsaves",	OPTION_MASK_ISA_XSAVES },
     { "-mmpx",          OPTION_MASK_ISA_MPX },
+    { "-mclwb",		OPTION_MASK_ISA_CLWB },
   };
 
   /* Flag options.  */
@@ -3157,6 +3158,7 @@ ix86_option_override_internal (bool main_args_p,
 #define PTA_AVX512VL		(HOST_WIDE_INT_1 << 52)
 #define PTA_AVX512IFMA		(HOST_WIDE_INT_1 << 53)
 #define PTA_AVX512VBMI		(HOST_WIDE_INT_1 << 54)
+#define PTA_CLWB		(HOST_WIDE_INT_1 << 55)
 
 #define PTA_CORE2 \
   (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
@@ -3716,6 +3718,9 @@ ix86_option_override_internal (bool main_args_p,
 	if (processor_alias_table[i].flags & PTA_PREFETCHWT1
 	    && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PREFETCHWT1))
 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1;
+	if (processor_alias_table[i].flags & PTA_CLWB
+	    && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLWB))
+	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB;
 	if (processor_alias_table[i].flags & PTA_CLFLUSHOPT
 	    && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLFLUSHOPT))
 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT;
@@ -4667,6 +4672,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
     IX86_ATTR_ISA ("xsaves",	OPT_mxsaves),
     IX86_ATTR_ISA ("avx512vbmi",	OPT_mavx512vbmi),
     IX86_ATTR_ISA ("avx512ifma",	OPT_mavx512ifma),
+    IX86_ATTR_ISA ("clwb",	OPT_mclwb),
 
     /* enum options */
     IX86_ATTR_ENUM ("fpmath=",	OPT_mfpmath_),
@@ -30128,6 +30134,9 @@ enum ix86_builtins
   IX86_BUILTIN_SHA256MSG2,
   IX86_BUILTIN_SHA256RNDS2,
 
+  /* CLWB instructions.  */
+  IX86_BUILTIN_CLWB,
+
   /* CLFLUSHOPT instructions.  */
   IX86_BUILTIN_CLFLUSHOPT,
 
@@ -33988,6 +33997,10 @@ ix86_init_mmx_sse_builtins (void)
   def_builtin (OPTION_MASK_ISA_CLFLUSHOPT, "__builtin_ia32_clflushopt",
 	       VOID_FTYPE_PCVOID, IX86_BUILTIN_CLFLUSHOPT);
 
+  /* CLWB.  */
+  def_builtin (OPTION_MASK_ISA_CLWB, "__builtin_ia32_clwb",
+	       VOID_FTYPE_PCVOID, IX86_BUILTIN_CLWB);
+
   /* Add FMA4 multi-arg argument instructions */
   for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
     {
@@ -38707,6 +38720,16 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
 	emit_insn (gen_sse2_clflush (op0));
 	return 0;
 
+    case IX86_BUILTIN_CLWB:
+	arg0 = CALL_EXPR_ARG (exp, 0);
+	op0 = expand_normal (arg0);
+	icode = CODE_FOR_clwb;
+	if (!insn_data[icode].operand[0].predicate (op0, Pmode))
+	  op0 = ix86_zero_extend_to_Pmode (op0);
+
+	emit_insn (gen_clwb (op0));
+	return 0;
+
     case IX86_BUILTIN_CLFLUSHOPT:
 	arg0 = CALL_EXPR_ARG (exp, 0);
 	op0 = expand_normal (arg0);
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 2596f812953..03d1b063e3e 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -150,6 +150,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_PREFETCHWT1_P(x)	TARGET_ISA_PREFETCHWT1_P(x)
 #define TARGET_MPX	TARGET_ISA_MPX
 #define TARGET_MPX_P(x)	TARGET_ISA_MPX_P(x)
+#define TARGET_CLWB	TARGET_ISA_CLWB
+#define TARGET_CLWB_P(x)	TARGET_ISA_CLWB_P(x)
 
 #define TARGET_LP64	TARGET_ABI_64
 #define TARGET_LP64_P(x)	TARGET_ABI_64_P(x)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 203db11ff06..a60e2de2782 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -253,6 +253,9 @@
 
   UNSPECV_NLGR
 
+  ;; For CLWB support
+  UNSPECV_CLWB
+
   ;; For CLFLUSHOPT support
   UNSPECV_CLFLUSHOPT
 ])
@@ -18668,6 +18671,15 @@
   [(set_attr "type" "other")
    (set_attr "length" "3")])
 
+(define_insn "clwb"
+  [(unspec_volatile [(match_operand 0 "address_operand" "p")]
+                   UNSPECV_CLWB)]
+  "TARGET_CLWB"
+  "clwb\t%a0"
+  [(set_attr "type" "sse")
+   (set_attr "atom_sse_attr" "fence")
+   (set_attr "memory" "unknown")])
+
 (define_insn "clflushopt"
   [(unspec_volatile [(match_operand 0 "address_operand" "p")]
                    UNSPECV_CLFLUSHOPT)]
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index f6ba8a7835b..2c7ca21224c 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -721,6 +721,10 @@ mclflushopt
 Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save
 Support CLFLUSHOPT instructions
 
+mclwb
+Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save
+Support CLWB instruction
+
 mfxsr
 Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save
 Support FXSAVE and FXRSTOR instructions
diff --git a/gcc/config/i386/x86intrin.h b/gcc/config/i386/x86intrin.h
index c84ab88c8c0..7f9a519d609 100644
--- a/gcc/config/i386/x86intrin.h
+++ b/gcc/config/i386/x86intrin.h
@@ -75,6 +75,8 @@
 
 #include <adxintrin.h>
 
+#include <clwbintrin.h>
+
 #include <clflushoptintrin.h>
 
 #include <xsavesintrin.h>