* LANGUAGES: Fix typos.

	* Makefile.in: Fix typos.
	* alias.c: Fix typos.
	* auto-inc-dec.c: Fix typos.
	* bb-reorder.c: Fix typos.
	* cfgcleanup.c: Fix typos.
	* cgraph.c: Fix typos.
	* cgraph.h: Fix typos.
	* cgraphunit.c: Fix typos.
	* collect2-aix.h: Fix typos.
	* collect2.c: Fix typos.
	* compare-elim.c: Fix typos.
	* config/alpha/vms.h: Fix typos.
	* config/arm/README-interworking: Fix typos.
	* config/arm/arm.c: Fix typos.
	* config/arm/iterators.md: Fix typos.
	* config/arm/vxworks.h: Fix typos.
	* config/avr/avr.c: Fix typos.
	* config/avr/avr.h: Fix typos.
	* config/avr/avr.md: Fix typos.
	* config/avr/builtins.def: Fix typos.
	* config/c6x/c6x.c: Fix typos.
	* config/cr16/cr16.c: Fix typos.
	* config/cr16/cr16.md: Fix typos.
	* config/cris/cris.md: Fix typos.
	* config/darwin.c: Fix typos.
	* config/darwin.opt: Fix typos.
	* config/i386/i386-c.c: Fix typos.
	* config/i386/i386.c: Fix typos.
	* config/ia64/ia64.c: Fix typos.
	* config/m68k/cf.md: Fix typos.
	* config/mep/mep.c: Fix typos.
	* config/microblaze/microblaze.c: Fix typos.
	* config/microblaze/microblaze.h: Fix typos.
	* config/mn10300/mn10300.c: Fix typos.
	* config/mn10300/mn10300.md: Fix typos.
	* config/pa/pa.c: Fix typos.
	* config/picochip/picochip.h: Fix typos.
	* config/rs6000/a2.md: Fix typos.
	* config/rs6000/rs6000.c: Fix typos.
	* config/rs6000/vector.md: Fix typos.
	* config/rx/rx.md: Fix typos.
	* config/rx/rx.opt: Fix typos.
	* config/s390/2097.md: Fix typos.
	* config/s390/s390.c: Fix typos.
	* config/s390/s390.h: Fix typos.
	* config/sh/sh.c: Fix typos.
	* config/sh/sh.md: Fix typos.
	* config/sparc/sync.md: Fix typos.
	* config/spu/spu.c: Fix typos.
	* config/spu/spu.md: Fix typos.
	* config/vms/vms.c: Fix typos.
	* config/vxworks-dummy.h: Fix typos.
	* config/vxworks.h: Fix typos.
	* cselib.c: Fix typos.
	* df-scan.c: Fix typos.
	* df.h: Fix typos.
	* doc/extend.texi: Fix typos.
	* doc/install.texi: Fix typos.
	* doc/invoke.texi: Fix typos.
	* doc/md.texi: Fix typos.
	* doc/plugins.texi: Fix typos.
	* doc/rtl.texi: Fix typos.
	* dse.c: Fix typos.
	* dwarf2asm.c: Fix typos.
	* dwarf2out.c: Fix typos.
	* except.h: Fix typos.
	* expr.c: Fix typos.
	* fold-const.c: Fix typos.
	* gcc.c: Fix typos.
	* gcse.c: Fix typos.
	* genautomata.c: Fix typos.
	* gengtype-state.c: Fix typos.
	* gengtype.c: Fix typos.
	* genhooks.c: Fix typos.
	* gimple-fold.c: Fix typos.
	* gimple-pretty-print.c: Fix typos.
	* gimple.c: Fix typos.
	* gimple.h: Fix typos.
	* gimplify.c: Fix typos.
	* graphite-interchange.c: Fix typos.
	* graphite-sese-to-poly.c: Fix typos.
	* ifcvt.c: Fix typos.
	* input.c: Fix typos.
	* ipa-cp.c: Fix typos.
	* ipa-inline-analysis.c: Fix typos.
	* ipa-inline-transform.c: Fix typos.
	* ipa-inline.c: Fix typos.
	* ipa-pure-const.c: Fix typos.
	* ipa-ref.h: Fix typos.
	* ipa-reference.c: Fix typos.
	* ipa-utils.c: Fix typos.
	* ipa.c: Fix typos.
	* ira-emit.c: Fix typos.
	* ira-lives.c: Fix typos.
	* lto-streamer.c: Fix typos.
	* lto-streamer.h: Fix typos.
	* lto-wrapper.c: Fix typos.
	* mcf.c: Fix typos.
	* mode-switching.c: Fix typos.
	* modulo-sched.c: Fix typos.
	* plugin.c: Fix typos.
	* postreload.c: Fix typos.
	* sched-deps.c: Fix typos.
	* sel-sched-ir.c: Fix typos.
	* sel-sched-ir.h: Fix typos.
	* sel-sched.c: Fix typos.
	* sese.c: Fix typos.
	* stor-layout.c: Fix typos.
	* target-hooks-macros.h: Fix typos.
	* target.def: Fix typos.
	* trans-mem.c: Fix typos.
	* tree-eh.c: Fix typos.
	* tree-predcom.c: Fix typos.
	* tree-sra.c: Fix typos.
	* tree-ssa-address.c: Fix typos.
	* tree-ssa-loop-ivopts.c: Fix typos.
	* tree-ssa-loop-niter.c: Fix typos.
	* tree-ssa-math-opts.c: Fix typos.
	* tree-ssa-pre.c: Fix typos.
	* tree-ssa-propagate.c: Fix typos.
	* tree-ssa-reassoc.c: Fix typos.
	* tree-ssa-sccvn.c: Fix typos.
	* tree-ssa-ter.c: Fix typos.
	* tree-ssa-uninit.c: Fix typos.
	* tree-ssanames.c: Fix typos.
	* tree-vect-generic.c: Fix typos.
	* tree-vect-slp.c: Fix typos.
	* tree.c: Fix typos.
	* tree.h: Fix typos.
	* varasm.c: Fix typos.
	* varpool.c: Fix typos.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@187959 138bc75d-0d04-0410-961f-82ee72b054a4

42 files changed, 60 insertions, 60 deletions

diff --git a/gcc/config/alpha/vms.h b/gcc/config/alpha/vms.h
index 6f90122fef3..03d9b9b229a 100644
--- a/gcc/config/alpha/vms.h
+++ b/gcc/config/alpha/vms.h
@@ -153,7 +153,7 @@ typedef struct {int num_args; enum avms_arg_type atypes[6];} avms_arg_info;
 
 #define DEFAULT_PCC_STRUCT_RETURN 0
 
-/* Eventhough pointers are 64bits, only 32bit ever remain significant in code
+/* Even though pointers are 64bits, only 32bit ever remain significant in code
    addresses.  */
 #define MASK_RETURN_ADDR                                \
   (flag_vms_pointer_size == VMS_POINTER_SIZE_NONE       \
diff --git a/gcc/config/arm/README-interworking b/gcc/config/arm/README-interworking
index 7f2eda83b49..cfa7f66e294 100644
--- a/gcc/config/arm/README-interworking
+++ b/gcc/config/arm/README-interworking
@@ -227,7 +227,7 @@ considerations when building programs and DLLs:
 
 Switching between the ARM and Thumb instruction sets is accomplished
 via the BX instruction which takes as an argument a register name.
-Control is transfered to the address held in this register (with the
+Control is transferred to the address held in this register (with the
 bottom bit masked out), and if the bottom bit is set, then Thumb
 instruction processing is enabled, otherwise ARM instruction
 processing is enabled.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 7a9819705e5..e2eebda958e 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2588,7 +2588,7 @@ optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
   int insns1, insns2;
   struct four_ints tmp_sequence;
 
-  /* If we aren't targetting ARM, the best place to start is always at
+  /* If we aren't targeting ARM, the best place to start is always at
      the bottom, otherwise look more closely.  */
   if (TARGET_ARM)
     {
@@ -8473,7 +8473,7 @@ cortex_a9_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
 			&& reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)),
 						    SET_DEST (PATTERN (dep))))
 		      {
-			/* FMACS is a special case where the dependant
+			/* FMACS is a special case where the dependent
 			   instruction can be issued 3 cycles before
 			   the normal latency in case of an output
 			   dependency.  */
@@ -16187,7 +16187,7 @@ arm_output_epilogue (rtx sibling)
 	 now we have to use add/sub in those cases. However, the value
 	 of that would be marginal, as both mov and add/sub are 32-bit
 	 in ARM mode, and it would require extra conditionals
-	 in arm_expand_prologue to distingish ARM-apcs-frame case
+	 in arm_expand_prologue to distinguish ARM-apcs-frame case
 	 (where frame pointer is required to point at first register)
 	 and ARM-non-apcs-frame. Therefore, such change is postponed
 	 until real need arise.  */
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 15672647e51..bb0d44e75e0 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -36,7 +36,7 @@
 ;; A list of integer modes that are less than a word
 (define_mode_iterator NARROW [QI HI])
 
-;; A list of all the integer modes upto 64bit
+;; A list of all the integer modes up to 64bit
 (define_mode_iterator QHSD [QI HI SI DI])
 
 ;; A list of the 32bit and 64bit integer modes
diff --git a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h
index 887691326e5..391c166336b 100644
--- a/gcc/config/arm/vxworks.h
+++ b/gcc/config/arm/vxworks.h
@@ -1,5 +1,5 @@
 /* Definitions of target machine for GCC,
-   for ARM with targetting the VXWorks run time environment. 
+   for ARM with targeting the VXWorks run time environment. 
    Copyright (C) 1999, 2000, 2003, 2004, 2007, 2008, 2009, 2010, 2011
    Free Software Foundation, Inc.
 
diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c
index 38afc7abf93..208f650c9af 100644
--- a/gcc/config/avr/avr.c
+++ b/gcc/config/avr/avr.c
@@ -6840,7 +6840,7 @@ avr_progmem_p (tree decl, tree attributes)
 /* Scan type TYP for pointer references to address space ASn.
    Return ADDR_SPACE_GENERIC (i.e. 0) if all pointers targeting
    the AS are also declared to be CONST.
-   Otherwise, return the respective addres space, i.e. a value != 0.  */
+   Otherwise, return the respective address space, i.e. a value != 0.  */
    
 static addr_space_t
 avr_nonconst_pointer_addrspace (tree typ)
@@ -6884,7 +6884,7 @@ avr_nonconst_pointer_addrspace (tree typ)
 }
 
 
-/* Sanity check NODE so that all pointers targeting non-generic addres spaces
+/* Sanity check NODE so that all pointers targeting non-generic address spaces
    go along with CONST qualifier.  Writing to these address spaces should
    be detected and complained about as early as possible.  */
 
@@ -9727,7 +9727,7 @@ avr_emit_movmemhi (rtx *xop)
   /* FIXME: Register allocator does a bad job and might spill address
         register(s) inside the loop leading to additional move instruction
         to/from stack which could clobber tmp_reg.  Thus, do *not* emit
-        load and store as seperate insns.  Instead, we perform the copy
+        load and store as separate insns.  Instead, we perform the copy
         by means of one monolithic insn.  */
 
   gcc_assert (TMP_REGNO == LPM_REGNO);
diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h
index 17867eb342e..54c127469e1 100644
--- a/gcc/config/avr/avr.h
+++ b/gcc/config/avr/avr.h
@@ -713,7 +713,7 @@ struct GTY(()) machine_function
   int attributes_checked_p;
 };
 
-/* AVR does not round pushes, but the existance of this macro is
+/* AVR does not round pushes, but the existence of this macro is
    required in order for pushes to be generated.  */
 #define PUSH_ROUNDING(X)	(X)
 
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 3fe06da661c..2b1a83c607a 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -29,7 +29,7 @@
 ;;  k  Reverse branch condition.
 ;;..m..Constant Direct Data memory address.
 ;;  i  Print the SFR address quivalent of a CONST_INT or a CONST_INT
-;;     RAM address.  The resulting addres is suitable to be used in IN/OUT.
+;;     RAM address.  The resulting address is suitable to be used in IN/OUT.
 ;;  o  Displacement for (mem (plus (reg) (const_int))) operands.
 ;;  p  POST_INC or PRE_DEC address as a pointer (X, Y, Z)
 ;;  r  POST_INC or PRE_DEC address as a register (r26, r28, r30)
diff --git a/gcc/config/avr/builtins.def b/gcc/config/avr/builtins.def
index 24537052eb0..4b04ff1b367 100644
--- a/gcc/config/avr/builtins.def
+++ b/gcc/config/avr/builtins.def
@@ -38,7 +38,7 @@ DEF_BUILTIN ("__builtin_avr_cli",   0, AVR_BUILTIN_CLI, void_ftype_void, CODE_FO
 DEF_BUILTIN ("__builtin_avr_wdr",   0, AVR_BUILTIN_WDR,   void_ftype_void, CODE_FOR_wdr)
 DEF_BUILTIN ("__builtin_avr_sleep", 0, AVR_BUILTIN_SLEEP, void_ftype_void, CODE_FOR_sleep)
 
-/* Mapped to respective instruction but might alse be folded away
+/* Mapped to respective instruction but might also be folded away
    or emit as libgcc call if ISA does not provide the instruction.  */
 DEF_BUILTIN ("__builtin_avr_swap",   1, AVR_BUILTIN_SWAP,   uchar_ftype_uchar,      CODE_FOR_rotlqi3_4)
 DEF_BUILTIN ("__builtin_avr_fmul",   2, AVR_BUILTIN_FMUL,   uint_ftype_uchar_uchar, CODE_FOR_fmul)
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index 8a368892bb2..a613bbae8e1 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -3630,7 +3630,7 @@ typedef struct c6x_sched_context
 /* The current scheduling state.  */
 static struct c6x_sched_context ss;
 
-/* The following variable value is DFA state before issueing the first insn
+/* The following variable value is DFA state before issuing the first insn
    in the current clock cycle.  This is used in c6x_variable_issue for
    comparison with the state after issuing the last insn in a cycle.  */
 static state_t prev_cycle_state;
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index 852c808f571..df272600c8b 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -61,7 +61,7 @@
 #define FUNC_IS_NORETURN_P(decl) (TREE_THIS_VOLATILE (decl))
 
 /* Predicate that holds when we need to save registers even for 'noreturn'
-   functions, to accomodate for unwinding.  */
+   functions, to accommodate for unwinding.  */
 #define MUST_SAVE_REGS_P() \
   (flag_unwind_tables || (flag_exceptions && !UI_SJLJ))
 
diff --git a/gcc/config/cr16/cr16.md b/gcc/config/cr16/cr16.md
index 5e4530c32ce..12072b46f0c 100644
--- a/gcc/config/cr16/cr16.md
+++ b/gcc/config/cr16/cr16.md
@@ -144,7 +144,7 @@
   [(set_attr "length" "2")]
 )
 
-;; Arithmetic Instuction  Patterns
+;; Arithmetic Instruction  Patterns
 
 ;; Addition-Subtraction "adddi3/subdi3" insns.
 (define_insn "<plusminus_insn>di3"
diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 49f36e350da..7d691f5a0b5 100644
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -1530,7 +1530,7 @@
   "movs<m> %1,%0"
   [(set_attr "slottable" "yes,yes,no")])
 
-;; To do a byte->word extension, extend to dword, exept that the top half
+;; To do a byte->word extension, extend to dword, except that the top half
 ;; of the register will be clobbered.  FIXME: Perhaps this is not needed.
 
 (define_insn "extendqihi2"
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 10cbdc39a3f..6805cf1264e 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -3461,7 +3461,7 @@ darwin_function_section (tree decl, enum node_frequency freq,
 
   /* Startup code should go to startup subsection unless it is
      unlikely executed (this happens especially with function splitting
-     where we can split away unnecesary parts of static constructors).  */
+     where we can split away unnecessary parts of static constructors).  */
   if (startup && freq != NODE_FREQUENCY_UNLIKELY_EXECUTED)
     return (weak)
 	    ? darwin_sections[text_startup_coal_section]
diff --git a/gcc/config/darwin.opt b/gcc/config/darwin.opt
index 3fcd35f090d..23419f9b0b1 100644
--- a/gcc/config/darwin.opt
+++ b/gcc/config/darwin.opt
@@ -224,7 +224,7 @@ Generate code suitable for fast turn around debugging
 ; and cc1plus don't crash if no -mmacosx-version-min is passed.  The
 ; driver will always pass a -mmacosx-version-min, so in normal use the
 ; Init is never used.  Useful for setting the OS on which people
-; ususally debug.
+; usually debug.
 mmacosx-version-min=
 Target Joined Report Var(darwin_macosx_version_min) Init("10.6")
 The earliest MacOS X version on which this program will run
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 23427bf034f..0f78d8928ed 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -48,7 +48,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
 			     void (*def_or_undef) (cpp_reader *,
 						   const char *))
 {
-  /* For some of the k6/pentium varients there weren't seperate ISA bits to
+  /* For some of the k6/pentium varients there weren't separate ISA bits to
      identify which tune/arch flag was passed, so figure it out here.  */
   size_t arch_len = strlen (ix86_arch_string);
   size_t tune_len = strlen (ix86_tune_string);
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 9e4ada03be4..30dbb089971 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -9185,7 +9185,7 @@ choose_baseaddr (HOST_WIDE_INT cfa_offset)
   if (m->use_fast_prologue_epilogue)
     {
       /* Choose the base register most likely to allow the most scheduling
-         opportunities.  Generally FP is valid througout the function,
+         opportunities.  Generally FP is valid throughout the function,
          while DRAP must be reloaded within the epilogue.  But choose either
          over the SP due to increased encoding size.  */
 
@@ -33112,7 +33112,7 @@ ix86_count_insn (basic_block bb)
   return min_prev_count;
 }
 
-/* Pad short funtion to 4 instructions.   */
+/* Pad short function to 4 instructions.   */
 
 static void
 ix86_pad_short_function (void)
@@ -36909,7 +36909,7 @@ expand_vec_perm_interleave2 (struct expand_vec_perm_d *d)
 	{
 	  if (d->perm[0] / nelt2 == nonzero_halves[1])
 	    {
-	      /* Attempt to increase the likelyhood that dfinal
+	      /* Attempt to increase the likelihood that dfinal
 		 shuffle will be intra-lane.  */
 	      char tmph = nonzero_halves[0];
 	      nonzero_halves[0] = nonzero_halves[1];
@@ -38985,7 +38985,7 @@ fits_dispatch_window (rtx insn)
   /* Make disp_cmp and disp_jcc get scheduled at the latest.  These
      instructions should be given the lowest priority in the
      scheduling process in Haifa scheduler to make sure they will be
-     scheduled in the same dispatch window as the refrence to them.  */
+     scheduled in the same dispatch window as the reference to them.  */
   if (group == disp_jcc || group == disp_cmp)
     return false;
 
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 8fb5b40da73..9a8bc0789c6 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -3454,7 +3454,7 @@ output_probe_stack_range (rtx reg1, rtx reg2)
    Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
    so that the debug info generation code can handle them properly.
 
-   The register save area is layed out like so:
+   The register save area is laid out like so:
    cfa+16
 	[ varargs spill area ]
 	[ fr register spill area ]
diff --git a/gcc/config/m68k/cf.md b/gcc/config/m68k/cf.md
index d6f1e92c3c9..96519dc9e4d 100644
--- a/gcc/config/m68k/cf.md
+++ b/gcc/config/m68k/cf.md
@@ -52,7 +52,7 @@
 
 (define_cpu_unit "cf_dsoc,cf_agex" "cfv123_oep")
 
-;; A memory unit that is reffered to as 'certain hardware resources' in
+;; A memory unit that is referred to as 'certain hardware resources' in
 ;; ColdFire reference manuals.  This unit remains occupied for two cycles
 ;; after last dsoc cycle of a store - hence there is a 2 cycle delay between
 ;; two consecutive stores.
diff --git a/gcc/config/mep/mep.c b/gcc/config/mep/mep.c
index edfff549e2a..f9ebab84048 100644
--- a/gcc/config/mep/mep.c
+++ b/gcc/config/mep/mep.c
@@ -3869,7 +3869,7 @@ static int prev_opcode = 0;
 
 /* This isn't as optimal as it could be, because we don't know what
    control register the STC opcode is storing in.  We only need to add
-   the nop if it's the relevent register, but we add it for irrelevent
+   the nop if it's the relevant register, but we add it for irrelevant
    registers also.  */
 
 void
@@ -6993,7 +6993,7 @@ core_insn_p (rtx insn)
 }
 
 /* Mark coprocessor instructions that can be bundled together with
-   the immediately preceeding core instruction.  This is later used
+   the immediately preceding core instruction.  This is later used
    to emit the "+" that tells the assembler to create a VLIW insn.
 
    For unbundled insns, the assembler will automatically add coprocessor
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index b170606bc75..081715d9823 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -190,7 +190,7 @@ enum reg_class microblaze_regno_to_class[] =
 /* MicroBlaze specific machine attributes.
    interrupt_handler - Interrupt handler attribute to add interrupt prologue 
 		       and epilogue and use appropriate interrupt return.
-   save_volatiles    - Similiar to interrupt handler, but use normal return.  */
+   save_volatiles    - Similar to interrupt handler, but use normal return.  */
 int interrupt_handler;
 int save_volatiles;
 
diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
index 92f0f60f1ff..d17d8948335 100644
--- a/gcc/config/microblaze/microblaze.h
+++ b/gcc/config/microblaze/microblaze.h
@@ -546,7 +546,7 @@ typedef struct microblaze_args
 
 #define FUNCTION_MODE   SImode
 
-/* Mode should alwasy be SImode */
+/* Mode should always be SImode */
 #define REGISTER_MOVE_COST(MODE, FROM, TO)			\
   ( GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? 2 		\
    : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4		\
diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c
index 1554f94644c..5b9f0699469 100644
--- a/gcc/config/mn10300/mn10300.c
+++ b/gcc/config/mn10300/mn10300.c
@@ -2762,7 +2762,7 @@ mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost)
       Chapter 3 of the MN103E Series Instruction Manual
       where it says:
 
-        "When the preceeding instruction is a CPU load or
+        "When the preceding instruction is a CPU load or
 	 store instruction, a following FPU instruction
 	 cannot be executed until the CPU completes the
 	 latency period even though there are no register
@@ -2788,7 +2788,7 @@ mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost)
     return cost;
 
   /* XXX: Verify: The text of 1-7-4 implies that the restriction
-     only applies when an INTEGER load/store preceeds an FPU
+     only applies when an INTEGER load/store precedes an FPU
      instruction, but is this true ?  For now we assume that it is.  */
   if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT)
     return cost;
diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
index 91378a79345..a1cbc7a9fd4 100644
--- a/gcc/config/mn10300/mn10300.md
+++ b/gcc/config/mn10300/mn10300.md
@@ -999,7 +999,7 @@
 ;; ??? Note that AM33 has a third multiply variant that puts the high part
 ;; into the MDRQ register, however this variant also constrains the inputs
 ;; to be in DATA_REGS and thus isn't as helpful as it might be considering
-;; the existance of the 4-operand multiply.  Nor is there a set of divide
+;; the existence of the 4-operand multiply.  Nor is there a set of divide
 ;; insns that use MDRQ.  Given that there is an IMM->MDRQ insn, this would
 ;; have been very handy for starting udivmodsi4...
 
@@ -1808,7 +1808,7 @@
 )
 
 ;; ----------------------------------------------------------------------
-;; MISCELANEOUS
+;; MISCELLANEOUS
 ;; ----------------------------------------------------------------------
 
 ;; Note the use of the (const_int 0) when generating the insn that matches
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 56c889db88c..a95d7037724 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -5939,7 +5939,7 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
 	}
 
       /* Request a secondary reload with a general scratch register
-	 for everthing else.  ??? Could symbolic operands be handled
+	 for everything else.  ??? Could symbolic operands be handled
 	 directly when generating non-pic PA 2.0 code?  */
       sri->icode = (in_p
 		    ? direct_optab_handler (reload_in_optab, mode)
diff --git a/gcc/config/picochip/picochip.h b/gcc/config/picochip/picochip.h
index abe6d6432b5..9eb7df94c01 100644
--- a/gcc/config/picochip/picochip.h
+++ b/gcc/config/picochip/picochip.h
@@ -221,7 +221,7 @@ extern enum picochip_dfa_type picochip_schedule_type;
 #define CALL_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,1, 1,1,1,1}
 #define CALL_REALLY_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,0, 0,1,0,0}
 
-/* Define the number of the picoChip link and condition psuedo registers. */
+/* Define the number of the picoChip link and condition pseudo registers. */
 #define LINK_REGNUM 12
 #define CC_REGNUM 17
 #define ACC_REGNUM 16
diff --git a/gcc/config/rs6000/a2.md b/gcc/config/rs6000/a2.md
index 851d8949ff7..79fdf913de1 100644
--- a/gcc/config/rs6000/a2.md
+++ b/gcc/config/rs6000/a2.md
@@ -25,7 +25,7 @@
 ;; The multiplier pipeline.
 (define_cpu_unit "mult" "ppca2")
 
-;; The auxillary processor unit (FP/vector unit).
+;; The auxiliary processor unit (FP/vector unit).
 (define_cpu_unit "axu" "ppca2")
 
 ;; D.4.6
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d7cb49db2d8..3d895390bcc 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2077,7 +2077,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
 
   /* TODO add SPE and paired floating point vector support.  */
 
-  /* Register class constaints for the constraints that depend on compile
+  /* Register class constraints for the constraints that depend on compile
      switches.  */
   if (TARGET_HARD_FLOAT && TARGET_FPRS)
     rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
@@ -2328,7 +2328,7 @@ darwin_rs6000_override_options (void)
 
   /* Unless the user (not the configurer) has explicitly overridden
      it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
-     G4 unless targetting the kernel.  */
+     G4 unless targeting the kernel.  */
   if (!flag_mkernel
       && !flag_apple_kext
       && strverscmp (darwin_macosx_version_min, "10.5") >= 0
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 6674054223b..87a52762a4d 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -172,7 +172,7 @@
 
 
 
-;; Reload patterns for vector operations.  We may need an addtional base
+;; Reload patterns for vector operations.  We may need an additional base
 ;; register to convert the reg+offset addressing to reg+reg for vector
 ;; registers and reg+reg or (reg+reg)&(-16) addressing to just an index
 ;; register for gpr registers.
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index 1ba603f4a6e..95ba051a486 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -408,7 +408,7 @@
 
 ;; Note - the following set of patterns do not use the "memory_operand"
 ;; predicate or an "m" constraint because we do not allow symbol_refs
-;; or label_refs as legitmate memory addresses.  This matches the
+;; or label_refs as legitimate memory addresses.  This matches the
 ;; behaviour of most of the RX instructions.  Only the call/branch
 ;; instructions are allowed to refer to symbols/labels directly.
 ;; The call operands are in QImode because that is the value of
diff --git a/gcc/config/rx/rx.opt b/gcc/config/rx/rx.opt
index 308bf0c8ada..76c2f61c79b 100644
--- a/gcc/config/rx/rx.opt
+++ b/gcc/config/rx/rx.opt
@@ -87,7 +87,7 @@ Use the simulator runtime.
 
 mas100-syntax
 Target Mask(AS100_SYNTAX) Report
-Generate assembler output that is compatible with the Renesas AS100 assembler.  This may restrict some of the compiler's capabilities.  The default is to generate GAS compatable syntax.
+Generate assembler output that is compatible with the Renesas AS100 assembler.  This may restrict some of the compiler's capabilities.  The default is to generate GAS compatible syntax.
 
 ;---------------------------------------------------
 
diff --git a/gcc/config/s390/2097.md b/gcc/config/s390/2097.md
index 77c206ecdbc..333e1b26ff4 100644
--- a/gcc/config/s390/2097.md
+++ b/gcc/config/s390/2097.md
@@ -703,11 +703,11 @@
 
 
 ; Declaration for some pseudo-pipeline stages that reflect the
-; dispatch gap when issueing an INT/FXU/BFU-executed instruction after
+; dispatch gap when issuing an INT/FXU/BFU-executed instruction after
 ; an instruction executed by a different unit has been executed.  The
 ; approach is that we pretend a pipelined execution of BFU operations
 ; with as many stages as the gap is long and request that none of
-; these stages is busy when issueing a FXU- or DFU-executed
+; these stages is busy when issuing a FXU- or DFU-executed
 ; instruction.  Similar for FXU- and DFU-executed instructions.
 
 ; Declaration for FPU stages.
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index b338cd96136..934e68b53a3 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -10533,7 +10533,7 @@ s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
 }
 
 /* This function is called via hook TARGET_SCHED_REORDER before
-   issueing one insn from list READY which contains *NREADYP entries.
+   issuing one insn from list READY which contains *NREADYP entries.
    For target z10 it reorders load instructions to avoid early load
    conflicts in the floating point pipeline  */
 static int
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 99c09e8860e..f69b3174b00 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -762,7 +762,7 @@ do {									\
 /* This value is used in tree-sra to decide whether it might benefical
    to split a struct move into several word-size moves.  For S/390
    only small values make sense here since struct moves are relatively
-   cheap thanks to mvc so the small default value choosen for archs
+   cheap thanks to mvc so the small default value chosen for archs
    with memmove patterns should be ok.  But this value is multiplied
    in tree-sra with UNITS_PER_WORD to make a decision so we adjust it
    here to compensate for that factor since mvc costs exactly the same
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 08ee5b436f5..048a7549739 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -393,7 +393,7 @@ static const struct attribute_spec sh_attribute_table[] =
    The insn that frees registers is most likely to be the insn with lowest
    LUID (original insn order); but such an insn might be there in the stalled
    queue (Q) instead of the ready queue (R).  To solve this, we skip cycles
-   upto a max of 8 cycles so that such insns may move from Q -> R.
+   up to a max of 8 cycles so that such insns may move from Q -> R.
 
    The description of the hooks are as below:
 
@@ -11478,7 +11478,7 @@ sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
    We could hold SFmode / SCmode values in XD registers, but that
    would require a tertiary reload when reloading from / to memory,
    and a secondary reload to reload from / to general regs; that
-   seems to be a loosing proposition.
+   seems to be a losing proposition.
 
    We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
    it won't be ferried through GP registers first.  */
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 7167b920641..99d4c625f23 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -577,7 +577,7 @@
   (and (eq_attr "type" "cbranch")
        (match_test "TARGET_SH2"))
   ;; SH2e has a hardware bug that pretty much prohibits the use of
-  ;; annuled delay slots.
+  ;; annulled delay slots.
   [(eq_attr "cond_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
 					  (not (eq_attr "cpu" "sh2e"))) (nil)])
 
@@ -631,7 +631,7 @@
   [(set_attr "type" "mt_group")])
 
 ;; Test low QI subreg against zero.
-;; This avoids unecessary zero extension before the test.
+;; This avoids unnecessary zero extension before the test.
 
 (define_insn "tstqi_t_zero"
   [(set (reg:SI T_REG)
@@ -5470,7 +5470,7 @@ label:
 ;; selected to copy QImode regs.  If one of them happens to be allocated
 ;; on the stack, reload will stick to movqi insn and generate wrong
 ;; displacement addressing because of the generic m alternatives.  
-;; With the movqi_reg_reg being specified before movqi it will be intially 
+;; With the movqi_reg_reg being specified before movqi it will be initially 
 ;; picked to load/store regs.  If the regs regs are on the stack reload will
 ;; try other insns and not stick to movqi_reg_reg.
 ;; The same applies to the movhi variants.
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index d07d572c614..d11f6636490 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -45,7 +45,7 @@
 })
 
 ;; A compiler-only memory barrier.  Generic code, when checking for the
-;; existance of various named patterns, uses asm("":::"memory") when we
+;; existence of various named patterns, uses asm("":::"memory") when we
 ;; don't need an actual instruction.  Here, it's easiest to pretend that
 ;; membar 0 is such a barrier.  Further, this gives us a nice hook to 
 ;; ignore all such barriers on Sparc V7.
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index dc5ca45dd57..fb482fb4c82 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -2870,7 +2870,7 @@ spu_machine_dependent_reorg (void)
 	    prop = prev;
 
 	  /* If this is the JOIN block of a simple IF-THEN then
-	     propogate the hint to the HEADER block. */
+	     propagate the hint to the HEADER block. */
 	  else if (prev && prev2
 		   && EDGE_COUNT (bb->preds) == 2
 		   && EDGE_COUNT (prev->preds) == 1
@@ -3124,7 +3124,7 @@ spu_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
 	prev_priority = INSN_PRIORITY (insn);
     }
 
-  /* Always try issueing more insns.  spu_sched_reorder will decide 
+  /* Always try issuing more insns.  spu_sched_reorder will decide 
      when the cycle should be advanced. */
   return 1;
 }
@@ -3231,7 +3231,7 @@ spu_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
      used to effect it. */
   if (in_spu_reorg && spu_dual_nops < 10)
     {
-      /* When we are at an even address and we are not issueing nops to
+      /* When we are at an even address and we are not issuing nops to
          improve scheduling then we need to advance the cycle.  */
       if ((spu_sched_length & 7) == 0 && prev_clock_var == clock
 	  && (spu_dual_nops == 0
diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index 3178a6df593..03ed4575591 100644
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -4209,7 +4209,7 @@ selb\t%0,%4,%0,%3"
   ""
   { spu_expand_prologue (); DONE; })
 
-;; "blockage" is only emited in epilogue.  This is what it took to
+;; "blockage" is only emitted in epilogue.  This is what it took to
 ;; make "basic block reordering" work with the insns sequence
 ;; generated by the spu_expand_epilogue (taken from mips.md)
 
diff --git a/gcc/config/vms/vms.c b/gcc/config/vms/vms.c
index d4ebd18730b..d23e8a8456a 100644
--- a/gcc/config/vms/vms.c
+++ b/gcc/config/vms/vms.c
@@ -99,12 +99,12 @@ static const struct vms_crtl_name vms_crtl_names[] =
 
 #define NBR_CRTL_NAMES (sizeof (vms_crtl_names) / sizeof (*vms_crtl_names))
 
-/* List of aliased identifiers.  They must be persistant accross gc.  */
+/* List of aliased identifiers.  They must be persistent across gc.  */
 
 static GTY(()) VEC(tree,gc) *aliases_id;
 
 /* Add a CRTL translation.  This simply use the transparent alias
-   mechanism, which is platform independant and works with the
+   mechanism, which is platform independent and works with the
    #pragma extern_prefix (which set the assembler name).  */
 
 static void
diff --git a/gcc/config/vxworks-dummy.h b/gcc/config/vxworks-dummy.h
index e3ea6ad6a98..e2ea7fa4d64 100644
--- a/gcc/config/vxworks-dummy.h
+++ b/gcc/config/vxworks-dummy.h
@@ -22,7 +22,7 @@ a copy of the GCC Runtime Library Exception along with this program;
 see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 <http://www.gnu.org/licenses/>.  */
 
-/* True if we're targetting VxWorks.  */
+/* True if we're targeting VxWorks.  */
 #ifndef TARGET_VXWORKS
 #define TARGET_VXWORKS 0
 #endif
diff --git a/gcc/config/vxworks.h b/gcc/config/vxworks.h
index 04ee945d650..000de3604f6 100644
--- a/gcc/config/vxworks.h
+++ b/gcc/config/vxworks.h
@@ -20,7 +20,7 @@ You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 
-/* Assert that we are targetting VxWorks.  */
+/* Assert that we are targeting VxWorks.  */
 #undef TARGET_VXWORKS
 #define TARGET_VXWORKS 1