ChangeLog: Follow spelling conventions.

	* ChangeLog: Follow spelling conventions.
	* ChangeLog.0: Likewise.
	* ChangeLog.1: Likewise.
	* ChangeLog.2: Likewise.
	* ChangeLog.3: Likewise.
	* ChangeLog.4: Likewise.
	* ChangeLog.5: Likewise.
	* ChangeLog.6: Likewise.
	* FSFChangeLog.10: Likewise.
	* FSFChangeLog.11: Likewise.
	* c-common.c: Likewise.
	* c-common.h: Likewise.
	* c-format.c: Likewise.
	* c-opts.c: Likewise.
	* cpplib.c: Likewise.
	* langhooks.h: Likewise.
	* real.c: Likewise.
	* reg-stack.c: Likewise.
	* toplev.c: Likewise.
	* config/arm/arm.c: Likewise.
	* config/arm/arm.md: Likewise.
	* config/arm/linux-gas.h: Likewise.
	* config/arm/netbsd.h: Likewise.
	* config/c4x/c4x.c: Likewise.
	* config/c4x/c4x.h: Likewise.
	* config/c4x/c4x.md: Likewise.
	* config/c4x/libgcc.S: Likewise.
	* config/fr30/fr30.md: Likewise.
	* config/frv/frv.md: Likewise.
	* config/ia64/ia64.md: Likewise.
	* config/mips/mips.h: Likewise.
	* config/mn10300/mn10300.c: Likewise.
	* config/stormy16/stormy16.c: Likewise.
	* config/v850/v850.md: Likewise.
	* doc/extend.texi: Likewise.
	* doc/invoke.texi: Likewise.
	* doc/md.texi: Likewise.

From-SVN: r57166

15 files changed, 25 insertions, 25 deletions

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a16fbe55c11..acdce8ebaf5 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -831,7 +831,7 @@ arm_isr_value (argument)
     if (streq (arg, ptr->arg))
       return ptr->return_value;
 
-  /* An unrecognised interrupt type.  */
+  /* An unrecognized interrupt type.  */
   return ARM_FT_UNKNOWN;
 }
 
@@ -1034,7 +1034,7 @@ arm_split_constant (code, mode, val, target, source, subtargets)
 	  && REGNO (target) != REGNO (source)))
     {
       /* After arm_reorg has been called, we can't fix up expensive
-	 constants by pushing them into memory so we must synthesise
+	 constants by pushing them into memory so we must synthesize
 	 them in-line, regardless of the cost.  This is only likely to
 	 be more costly on chips that have load delay slots and we are
 	 compiling without running the scheduler (so no splitting
@@ -7859,7 +7859,7 @@ emit_multi_reg_push (mask)
     num_dwarf_regs--;
 
   /* For the body of the insn we are going to generate an UNSPEC in
-     parallel with several USEs.  This allows the insn to be recognised
+     parallel with several USEs.  This allows the insn to be recognized
      by the push_multi pattern in the arm.md file.  The insn looks
      something like this:
 
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 8d58b529d1c..7c739301153 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3913,7 +3913,7 @@
 ;;  DONE;
 ;;}")
 
-;; Recognise garbage generated above.
+;; Recognize garbage generated above.
 
 ;;(define_insn ""
 ;;  [(set (match_operand:TI 0 "general_operand" "=r,r,r,<,>,m")
@@ -4682,7 +4682,7 @@
   "
 )
 
-;; Pattern to recognise insn generated default case above
+;; Pattern to recognize insn generated default case above
 (define_insn "*movhi_insn_arch4"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")    
 	(match_operand:HI 1 "general_operand"      "rI,K,r,m"))]
diff --git a/gcc/config/arm/linux-gas.h b/gcc/config/arm/linux-gas.h
index b4e346dd9ef..5e8ddf91ca2 100644
--- a/gcc/config/arm/linux-gas.h
+++ b/gcc/config/arm/linux-gas.h
@@ -45,7 +45,7 @@ Boston, MA 02111-1307, USA.  */
 #undef  WCHAR_TYPE_SIZE
 #define WCHAR_TYPE_SIZE BITS_PER_WORD
 
-/* Emit code to set up a trampoline and synchronise the caches.  */
+/* Emit code to set up a trampoline and synchronize the caches.  */
 #undef  INITIALIZE_TRAMPOLINE
 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
 {									\
diff --git a/gcc/config/arm/netbsd.h b/gcc/config/arm/netbsd.h
index e5582673671..ac6da05105b 100644
--- a/gcc/config/arm/netbsd.h
+++ b/gcc/config/arm/netbsd.h
@@ -148,7 +148,7 @@ Boston, MA 02111-1307, USA.  */
 #undef  DEFAULT_STRUCTURE_SIZE_BOUNDARY
 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 8
 
-/* Emit code to set up a trampoline and synchronise the caches.  */
+/* Emit code to set up a trampoline and synchronize the caches.  */
 #undef  INITIALIZE_TRAMPOLINE
 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)                      \
 {                                                                      \
diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c
index 79096657da4..0ea79a6cf08 100644
--- a/gcc/config/c4x/c4x.c
+++ b/gcc/config/c4x/c4x.c
@@ -1469,7 +1469,7 @@ c4x_check_legit_addr (mode, addr, strict)
   switch (code)
     {
       /* Register indirect with auto increment/decrement.  We don't
-	 allow SP here---push_operand should recognise an operand
+	 allow SP here---push_operand should recognize an operand
 	 being pushed on the stack.  */
 
     case PRE_DEC:
diff --git a/gcc/config/c4x/c4x.h b/gcc/config/c4x/c4x.h
index 04d6949a7f8..94cca09b597 100644
--- a/gcc/config/c4x/c4x.h
+++ b/gcc/config/c4x/c4x.h
@@ -1470,7 +1470,7 @@ CUMULATIVE_ARGS;
 
    Note that we return, rather than break so that rtx_cost doesn't
    include CONST_COSTS otherwise expand_mult will think that it is
-   cheaper to synthesise a multiply rather than to use a multiply
+   cheaper to synthesize a multiply rather than to use a multiply
    instruction.  I think this is because the algorithm synth_mult
    doesn't take into account the loading of the operands, whereas the
    calculation of mult_cost does. 
diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md
index b9ac85cffe8..2d52082da35 100644
--- a/gcc/config/c4x/c4x.md
+++ b/gcc/config/c4x/c4x.md
@@ -29,7 +29,7 @@
 ;        for QImode and Pmode, whether Pmode was QImode or PQImode.
 ;        For addresses we wouldn't have to have a clobber of the CC
 ;        associated with each insn and we could use MPYI in address
-;        calculations without having to synthesise a proper 32 bit multiply.
+;        calculations without having to synthesize a proper 32 bit multiply.
 
 ; Additional C30/C40 instructions not coded:
 ; CALLcond, IACK, IDLE, LDE, LDFI, LDII, LDM, NORM, RETIcond
@@ -1360,7 +1360,7 @@
 ;  If one of the operands is not a register, then we should
 ;  emit two insns, using a scratch register.  This will produce
 ;  better code in loops if the source operand is invariant, since
-;  the source reload can be optimised out.  During reload we cannot
+;  the source reload can be optimized out.  During reload we cannot
 ;  use change_address or force_reg which will allocate new pseudo regs.
 
 ;  Unlike most other insns, the move insns can't be split with
@@ -2076,7 +2076,7 @@
      {        
        if (GET_CODE (operands[2]) == CONST_INT)
          {
-          /* Let GCC try to synthesise the multiplication using shifts
+          /* Let GCC try to synthesize the multiplication using shifts
              and adds.  In most cases this will be more profitable than
              using the C3x MPYI.  */
             FAIL;
@@ -3410,7 +3410,7 @@
 ;  If one of the operands is not a register, then we should
 ;  emit two insns, using a scratch register.  This will produce
 ;  better code in loops if the source operand is invariant, since
-;  the source reload can be optimised out.  During reload we cannot
+;  the source reload can be optimized out.  During reload we cannot
 ;  use change_address or force_reg.
 (define_expand "movqf"
   [(set (match_operand:QF 0 "src_operand" "")
@@ -5317,7 +5317,7 @@
 ; Note we have to emit a dbu instruction if there are no delay slots
 ; to fill.
 ; Also note that GCC will try to reverse a loop to see if it can
-; utilise this instruction.  However, if there are more than one
+; utilize this instruction.  However, if there are more than one
 ; memory reference in the loop, it cannot guarantee that reversing
 ; the loop will work :(  (see check_dbra_loop() in loop.c)
 ; Note that the C3x only decrements the 24 LSBs of the address register
@@ -5629,7 +5629,7 @@
 
 ; The current low overhead looping code is naff and is not failsafe
 ; If you want RTPB instructions to be generated, apply the patches
-; from www.elec.canterbury.ac.nz/c4x.  This will utilise the
+; from www.elec.canterbury.ac.nz/c4x.  This will utilize the
 ; doloop_begin and doloop_end patterns in this MD.
 (define_expand "decrement_and_branch_on_count"
   [(parallel [(set (pc)
@@ -7315,7 +7315,7 @@
 
 ; The following two peepholes remove an unecessary load
 ; often found at the end of a function.  These peepholes
-; could be generalised to other binary operators.  They shouldn't
+; could be generalized to other binary operators.  They shouldn't
 ; be required if we run a post reload mop-up pass.
 (define_peephole
  [(parallel [(set (match_operand:QF 0 "ext_reg_operand" "")
diff --git a/gcc/config/c4x/libgcc.S b/gcc/config/c4x/libgcc.S
index 96b27d862ca..0335a0e217e 100644
--- a/gcc/config/c4x/libgcc.S
+++ b/gcc/config/c4x/libgcc.S
@@ -48,7 +48,7 @@ Boston, MA 02111-1307, USA.  */
 ;
 ; r[i + 1] = r[i] * (2.0 - v * r[i])
 ;
-; The normalised error e[i] at the ith iteration is
+; The normalized error e[i] at the ith iteration is
 ;
 ; e[i] = (r - r[i]) / r = (1 / v - r[i]) * v = (1 - v * r[i])
 ;
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
index 8557ce898d2..9c9a8bdeeea 100644
--- a/gcc/config/fr30/fr30.md
+++ b/gcc/config/fr30/fr30.md
@@ -521,7 +521,7 @@
 ;;{{{ Floating Point Moves 
 
 ;; Note - Patterns for SF mode moves are compulsory, but
-;; patterns for DF are optional, as GCC can synthesise them.
+;; patterns for DF are optional, as GCC can synthesize them.
 
 (define_expand "movsf"
   [(set (match_operand:SF 0 "general_operand" "")
diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index f1668045242..ac078ba9b2c 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -1607,7 +1607,7 @@
 ;; Floating Point Moves
 ;;
 ;; Note - Patterns for SF mode moves are compulsory, but
-;; patterns for DF are optional, as GCC can synthesise them.
+;; patterns for DF are optional, as GCC can synthesize them.
 
 (define_expand "movsf"
   [(set (match_operand:SF 0 "general_operand" "")
@@ -2258,7 +2258,7 @@
 ;; Signed conversions from a smaller integer to a larger integer
 ;;
 ;; These operations are optional.  If they are not
-;; present GCC will synthesise them for itself
+;; present GCC will synthesize them for itself
 ;; Even though frv does not provide these instructions, we define them
 ;; to allow load + sign extend to be collapsed together
 (define_insn "extendqihi2"
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 75a36b3a1a0..1275acdc17e 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -766,7 +766,7 @@
 ;; Floating Point Moves
 ;;
 ;; Note - Patterns for SF mode moves are compulsory, but
-;; patterns for DF are optional, as GCC can synthesise them.
+;; patterns for DF are optional, as GCC can synthesize them.
 
 (define_expand "movsf"
   [(set (match_operand:SF 0 "general_operand" "")
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index c04e6b51a21..73d941adcc0 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -123,7 +123,7 @@ enum block_move_type {
   BLOCK_MOVE_LAST			/* generate just the last store */
 };
 
-/* Information about one recognised processor.  Defined here for the
+/* Information about one recognized processor.  Defined here for the
    benefit of TARGET_CPU_CPP_BUILTINS.  */
 struct mips_cpu_info {
   /* The 'canonical' name of the processor as far as GCC is concerned.
diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c
index 52284c0d3f7..49b59b112e3 100644
--- a/gcc/config/mn10300/mn10300.c
+++ b/gcc/config/mn10300/mn10300.c
@@ -647,7 +647,7 @@ notice_update_cc (body, insn)
     }
 }
 
-/* Recognise the PARALLEL rtx generated by mn10300_gen_multiple_store().
+/* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
    This function is for MATCH_PARALLEL and so assumes OP is known to be
    parallel.  If OP is a multiple store, return a mask indicating which
    registers it saves.  Return 0 otherwise.  */
diff --git a/gcc/config/stormy16/stormy16.c b/gcc/config/stormy16/stormy16.c
index 6b9f153e789..1e2813cb2a5 100644
--- a/gcc/config/stormy16/stormy16.c
+++ b/gcc/config/stormy16/stormy16.c
@@ -476,7 +476,7 @@ xstormy16_secondary_reload_class (class, mode, x)
   return NO_REGS;
 }
 
-/* Recognise a PLUS that needs the carry register.  */
+/* Recognize a PLUS that needs the carry register.  */
 int
 xstormy16_carry_plus_operand (x, mode)
      rtx x;
diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md
index 96ece9cfac6..20a22c750a7 100644
--- a/gcc/config/v850/v850.md
+++ b/gcc/config/v850/v850.md
@@ -851,7 +851,7 @@
 ;; ??? This is very ugly.  The right way to do this is to modify cmpsi so
 ;; that it doesn't emit RTL, and then modify the bcc/scc patterns so that
 ;; they emit RTL for the compare instruction.  Unfortunately, this requires
-;; lots of changes that will be hard to sanitise.  So for now, cmpsi still
+;; lots of changes that will be hard to sanitize.  So for now, cmpsi still
 ;; emits RTL, and I get the compare operands here from the previous insn.
 
 (define_expand "movsicc"