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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2017-03-02 19:17:04 +0000 |
|---|---|---|
| committer | William Schmidt <wschmidt@gcc.gnu.org> | 2017-03-02 19:17:04 +0000 |
| commit | d36a53d6f20d6f689b4e0cc9485103b8f71fe33f (patch) | |
| tree | 072400f8a14822a155cae3fbcf83ad1c0181d565 /gcc/config | |
| parent | 1a5a334e7839b2fe8a200c60af066e836ceff12c (diff) | |
| download | gcc-d36a53d6f20d6f689b4e0cc9485103b8f71fe33f.tar.gz | |
vector.md (vector_ne_<mode>_p): Correct operand numbers.
2017-03-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/vector.md (vector_ne_<mode>_p): Correct operand
numbers.
(vector_ae_<mode>_p): Likewise.
(vector_nez_<mode>_p): Likewise.
(vector_ne_v2di_p): Likewise.
(vector_ae_v2di_p): Likewise.
(vector_ne_<mode>_p): Likewise.
* config/rs6000/vsx.md (vsx_tsqrt<mode>2_fg): Correct operand
numbers.
(vsx_tsqrt<mode>2_fe): Likewise.
From-SVN: r245849
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/rs6000/vector.md | 24 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 12 |
2 files changed, 18 insertions, 18 deletions
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index ef6bd14b2b1..fefe5db6aae 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -700,7 +700,7 @@ (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand") (match_operand:VI 2 "vlogical_operand"))] UNSPEC_PREDICATE)) - (set (match_dup 4) + (set (match_dup 3) (ne:VI (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 0 "register_operand" "=r") @@ -708,7 +708,7 @@ (const_int 0)))] "TARGET_P9_VECTOR" { - operands[4] = gen_reg_rtx (<MODE>mode); + operands[3] = gen_reg_rtx (<MODE>mode); }) ;; This expansion handles the V16QI, V8HI, and V4SI modes in the @@ -719,7 +719,7 @@ (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand") (match_operand:VI 2 "vlogical_operand"))] UNSPEC_PREDICATE)) - (set (match_dup 4) + (set (match_dup 3) (ne:VI (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 0 "register_operand" "=r") @@ -730,7 +730,7 @@ (const_int 1)))] "TARGET_P9_VECTOR" { - operands[4] = gen_reg_rtx (<MODE>mode); + operands[3] = gen_reg_rtx (<MODE>mode); }) ;; This expansion handles the V16QI, V8HI, and V4SI modes in the @@ -763,7 +763,7 @@ (unspec:CC [(eq:CC (match_operand:V2DI 1 "vlogical_operand") (match_operand:V2DI 2 "vlogical_operand"))] UNSPEC_PREDICATE)) - (set (match_dup 4) + (set (match_dup 3) (eq:V2DI (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 0 "register_operand" "=r") @@ -771,7 +771,7 @@ (const_int 0)))] "TARGET_P9_VECTOR" { - operands[4] = gen_reg_rtx (V2DImode); + operands[3] = gen_reg_rtx (V2DImode); }) ;; This expansion handles the V2DI mode in the implementation of the @@ -786,7 +786,7 @@ (unspec:CC [(eq:CC (match_operand:V2DI 1 "vlogical_operand") (match_operand:V2DI 2 "vlogical_operand"))] UNSPEC_PREDICATE)) - (set (match_dup 4) + (set (match_dup 3) (eq:V2DI (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 0 "register_operand" "=r") @@ -797,7 +797,7 @@ (const_int 1)))] "TARGET_P9_VECTOR" { - operands[4] = gen_reg_rtx (V2DImode); + operands[3] = gen_reg_rtx (V2DImode); }) ;; This expansion handles the V4SF and V2DF modes in the Power9 @@ -811,7 +811,7 @@ (unspec:CC [(eq:CC (match_operand:VEC_F 1 "vlogical_operand") (match_operand:VEC_F 2 "vlogical_operand"))] UNSPEC_PREDICATE)) - (set (match_dup 4) + (set (match_dup 3) (eq:VEC_F (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 0 "register_operand" "=r") @@ -819,7 +819,7 @@ (const_int 0)))] "TARGET_P9_VECTOR" { - operands[4] = gen_reg_rtx (<MODE>mode); + operands[3] = gen_reg_rtx (<MODE>mode); }) ;; This expansion handles the V4SF and V2DF modes in the Power9 @@ -833,7 +833,7 @@ (unspec:CC [(eq:CC (match_operand:VEC_F 1 "vlogical_operand") (match_operand:VEC_F 2 "vlogical_operand"))] UNSPEC_PREDICATE)) - (set (match_dup 4) + (set (match_dup 3) (eq:VEC_F (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 0 "register_operand" "=r") @@ -844,7 +844,7 @@ (const_int 1)))] "TARGET_P9_VECTOR" { - operands[4] = gen_reg_rtx (<MODE>mode); + operands[3] = gen_reg_rtx (<MODE>mode); }) (define_expand "vector_gt_<mode>_p" diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 111c2e8214b..aabc8f61ece 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1383,28 +1383,28 @@ ;; *tsqrt* returning the fg flag (define_expand "vsx_tsqrt<mode>2_fg" - [(set (match_dup 3) + [(set (match_dup 2) (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")] UNSPEC_VSX_TSQRT)) (set (match_operand:SI 0 "gpc_reg_operand" "") - (gt:SI (match_dup 3) + (gt:SI (match_dup 2) (const_int 0)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" { - operands[3] = gen_reg_rtx (CCFPmode); + operands[2] = gen_reg_rtx (CCFPmode); }) ;; *tsqrt* returning the fe flag (define_expand "vsx_tsqrt<mode>2_fe" - [(set (match_dup 3) + [(set (match_dup 2) (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")] UNSPEC_VSX_TSQRT)) (set (match_operand:SI 0 "gpc_reg_operand" "") - (eq:SI (match_dup 3) + (eq:SI (match_dup 2) (const_int 0)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" { - operands[3] = gen_reg_rtx (CCFPmode); + operands[2] = gen_reg_rtx (CCFPmode); }) (define_insn "*vsx_tsqrt<mode>2_internal" |