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| author | Uros Bizjak <uros@gcc.gnu.org> | 2011-11-01 22:36:30 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2011-11-01 22:36:30 +0100 |
| commit | c2a8964176acaf6c08c68c1dfa34234bd63ba5be (patch) | |
| tree | 79cbfd9b0fd30cec898d98c9c16e537cd0d0c360 /gcc/config | |
| parent | 6bf39801d477bd03305ac582bac8331301808da9 (diff) | |
| download | gcc-c2a8964176acaf6c08c68c1dfa34234bd63ba5be.tar.gz | |
i386.md (splitters for int-float conversion): Use reg_or_subregno in splitter constraints.
* config/i386/i386.md (splitters for int-float conversion): Use
reg_or_subregno in splitter constraints.
From-SVN: r180745
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.md | 36 |
1 files changed, 9 insertions, 27 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index a8ebfa48000..4fae10d4aec 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -4920,9 +4920,7 @@ && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387 && TARGET_INTER_UNIT_CONVERSIONS && reload_completed - && (SSE_REG_P (operands[0]) - || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REGNO_P (reg_or_subregno (operands[0]))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_split @@ -4933,9 +4931,7 @@ && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387 && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && reload_completed - && (SSE_REG_P (operands[0]) - || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REGNO_P (reg_or_subregno (operands[0]))" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (float:MODEF (match_dup 2)))]) @@ -5024,9 +5020,7 @@ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed - && (SSE_REG_P (operands[0]) - || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REGNO_P (reg_or_subregno (operands[0]))" [(const_int 0)] { rtx op1 = operands[1]; @@ -5067,9 +5061,7 @@ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed - && (SSE_REG_P (operands[0]) - || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REGNO_P (reg_or_subregno (operands[0]))" [(const_int 0)] { operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0], @@ -5091,9 +5083,7 @@ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed - && (SSE_REG_P (operands[0]) - || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REGNO_P (reg_or_subregno (operands[0]))" [(const_int 0)] { rtx op1 = operands[1]; @@ -5137,9 +5127,7 @@ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed - && (SSE_REG_P (operands[0]) - || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REGNO_P (reg_or_subregno (operands[0]))" [(const_int 0)] { operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0], @@ -5200,9 +5188,7 @@ && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && reload_completed - && (SSE_REG_P (operands[0]) - || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REGNO_P (reg_or_subregno (operands[0]))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit" @@ -5235,9 +5221,7 @@ && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && reload_completed - && (SSE_REG_P (operands[0]) - || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REGNO_P (reg_or_subregno (operands[0]))" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (float:MODEF (match_dup 2)))]) @@ -5248,9 +5232,7 @@ "(<SWI48x:MODE>mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && reload_completed - && (SSE_REG_P (operands[0]) - || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REGNO_P (reg_or_subregno (operands[0]))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387_with_temp" |