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| author | David S. Miller <davem@davemloft.net> | 2012-11-07 08:42:09 +0000 |
|---|---|---|
| committer | David S. Miller <davem@gcc.gnu.org> | 2012-11-07 00:42:09 -0800 |
| commit | aaa050aa4a13eb045ae5db57d8a50a5b4121c29e (patch) | |
| tree | 65a9d61bd04f3a4a556b5898fadfa79341f0b5d4 /gcc/config/sparc/sparc.md | |
| parent | 9ac37178e3e934cad54be545e6a55fa067d80270 (diff) | |
| download | gcc-aaa050aa4a13eb045ae5db57d8a50a5b4121c29e.tar.gz | |
Revert sparc "U" constraint removal.
PR bootstrap/55211
Revert:
* config/sparc/constraints.md ("U"): Delete.
* config/sparc/sparc.md: Use 'r' constraint instead of 'U'.
* config/sparc/sync.md: Likewise.
And revert parts of:
* doc/md.texi: Sync sparc constraint documentation with reality.
From-SVN: r193283
Diffstat (limited to 'gcc/config/sparc/sparc.md')
| -rw-r--r-- | gcc/config/sparc/sparc.md | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 4a44078a26c..f604f46610e 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1595,9 +1595,9 @@ (define_insn "*movdi_insn_sp32" [(set (match_operand:DI 0 "nonimmediate_operand" - "=T,o,T,r,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b") + "=T,o,T,U,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b") (match_operand:DI 1 "input_operand" - " J,J,r,T,r,o,i,r,*f, T, o,*f, *e, *e,?*f, r, W,*e,J,P"))] + " J,J,U,T,r,o,i,r,*f, T, o,*f, *e, *e,?*f, r, W,*e,J,P"))] "! TARGET_ARCH64 && (register_operand (operands[0], DImode) || register_or_zero_operand (operands[1], DImode))" @@ -2302,8 +2302,8 @@ }) (define_insn "*movdf_insn_sp32" - [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,e,*r, f, e,T,W,r,T, f, *r, o,o") - (match_operand:DF 1 "input_operand" "G,C,e,e, f,*r,W#F,G,e,T,r,o#F,*roF,*rG,f"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,e,*r, f, e,T,W,U,T, f, *r, o,o") + (match_operand:DF 1 "input_operand" "G,C,e,e, f,*r,W#F,G,e,T,U,o#F,*roF,*rG,f"))] "! TARGET_ARCH64 && (register_operand (operands[0], DFmode) || register_or_zero_or_all_ones_operand (operands[1], DFmode))" @@ -2541,8 +2541,8 @@ }) (define_insn "*movtf_insn_sp32" - [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o,r, r") - (match_operand:TF 1 "input_operand" " G,oe,e,rG,o,roG"))] + [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o,U, r") + (match_operand:TF 1 "input_operand" " G,oe,e,rGU,o,roG"))] "! TARGET_ARCH64 && (register_operand (operands[0], TFmode) || register_or_zero_operand (operands[1], TFmode))" @@ -7911,8 +7911,8 @@ (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*")]) (define_insn "*mov<VM64:mode>_insn_sp32" - [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,*r, f,e,m,m,r,T, o,*r") - (match_operand:VM64 1 "input_operand" "Y,C,e, f,*r,m,e,Y,T,r,*r,*r"))] + [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,*r, f,e,m,m,U,T, o,*r") + (match_operand:VM64 1 "input_operand" "Y,C,e, f,*r,m,e,Y,T,U,*r,*r"))] "TARGET_VIS && ! TARGET_ARCH64 && (register_operand (operands[0], <VM64:MODE>mode) |