diff options
| author | Eric Botcazou <ebotcazou@adacore.com> | 2013-05-28 07:26:35 +0000 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@gcc.gnu.org> | 2013-05-28 07:26:35 +0000 |
| commit | 5c3eacbbdb118b63ee65b1774a9d1b003afed908 (patch) | |
| tree | 0690ee378a242808ef4348577f657b3c0e03b1f3 /gcc/config/sparc/sparc.md | |
| parent | eb9b2285911d52a5db151c816b93883b79119a6f (diff) | |
| download | gcc-5c3eacbbdb118b63ee65b1774a9d1b003afed908.tar.gz | |
invoke.texi (SPARC Options): Document -mfix-ut699.
* doc/invoke.texi (SPARC Options): Document -mfix-ut699.
* builtins.c (expand_builtin_mathfn) <BUILT_IN_SQRT>: Try to widen the
mode if the instruction isn't available in the original mode.
* config/sparc/sparc.opt (mfix-ut699): New option.
* config/sparc/sparc.md (muldf3_extend): Disable if -mfix-ut699.
(divdf3): Turn into expander.
(divdf3_nofix): New insn.
(divdf3_fix): Likewise.
(divsf3): Disable if -mfix-ut699.
(sqrtdf2): Turn into expander.
(sqrtdf2_nofix): New insn.
(sqrtdf2_fix): Likewise.
(sqrtsf2): Disable if -mfix-ut699.
From-SVN: r199366
Diffstat (limited to 'gcc/config/sparc/sparc.md')
| -rw-r--r-- | gcc/config/sparc/sparc.md | 42 |
1 files changed, 37 insertions, 5 deletions
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 292cb205271..f710cc7b6b2 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -5499,7 +5499,7 @@ [(set (match_operand:DF 0 "register_operand" "=e") (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f")) (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))] - "(TARGET_V8 || TARGET_V9) && TARGET_FPU" + "(TARGET_V8 || TARGET_V9) && TARGET_FPU && !sparc_fix_ut699" "fsmuld\t%1, %2, %0" [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) @@ -5528,20 +5528,37 @@ "fdivq\t%1, %2, %0" [(set_attr "type" "fpdivd")]) -(define_insn "divdf3" +(define_expand "divdf3" [(set (match_operand:DF 0 "register_operand" "=e") (div:DF (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" + "") + +(define_insn "*divdf3_nofix" + [(set (match_operand:DF 0 "register_operand" "=e") + (div:DF (match_operand:DF 1 "register_operand" "e") + (match_operand:DF 2 "register_operand" "e")))] + "TARGET_FPU && !sparc_fix_ut699" "fdivd\t%1, %2, %0" [(set_attr "type" "fpdivd") (set_attr "fptype" "double")]) +(define_insn "*divdf3_fix" + [(set (match_operand:DF 0 "register_operand" "=e") + (div:DF (match_operand:DF 1 "register_operand" "e") + (match_operand:DF 2 "register_operand" "e")))] + "TARGET_FPU && sparc_fix_ut699" + "fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]" + [(set_attr "type" "fpdivd") + (set_attr "fptype" "double") + (set_attr "length" "2")]) + (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=f") (div:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] - "TARGET_FPU" + "TARGET_FPU && !sparc_fix_ut699" "fdivs\t%1, %2, %0" [(set_attr "type" "fpdivs")]) @@ -5742,18 +5759,33 @@ "fsqrtq\t%1, %0" [(set_attr "type" "fpsqrtd")]) -(define_insn "sqrtdf2" +(define_expand "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "=e") (sqrt:DF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU" + "") + +(define_insn "*sqrtdf2_nofix" + [(set (match_operand:DF 0 "register_operand" "=e") + (sqrt:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && !sparc_fix_ut699" "fsqrtd\t%1, %0" [(set_attr "type" "fpsqrtd") (set_attr "fptype" "double")]) +(define_insn "*sqrtdf2_fix" + [(set (match_operand:DF 0 "register_operand" "=e") + (sqrt:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && sparc_fix_ut699" + "fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]" + [(set_attr "type" "fpsqrtd") + (set_attr "fptype" "double") + (set_attr "length" "2")]) + (define_insn "sqrtsf2" [(set (match_operand:SF 0 "register_operand" "=f") (sqrt:SF (match_operand:SF 1 "register_operand" "f")))] - "TARGET_FPU" + "TARGET_FPU && !sparc_fix_ut699" "fsqrts\t%1, %0" [(set_attr "type" "fpsqrts")]) |