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| author | uweigand <uweigand@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-03-21 20:03:10 +0000 |
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| committer | uweigand <uweigand@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-03-21 20:03:10 +0000 |
| commit | 401fe9a1c76dbfc38368b14392299c3759bc277b (patch) | |
| tree | 72db31cf2df5fb94c64e6f495638245a6623a58c /gcc/config/s390 | |
| parent | e4fedb1070360ac800a485c1cde655321cab1474 (diff) | |
| download | gcc-401fe9a1c76dbfc38368b14392299c3759bc277b.tar.gz | |
* config/s390/s390.md ("addti3", "subti3"): New insns and splitters.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@79793 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/s390')
| -rw-r--r-- | gcc/config/s390/s390.md | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 5e139803926..8348c5a2791 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -3331,6 +3331,35 @@ ;; ; +; addti3 instruction pattern(s). +; + +(define_insn_and_split "addti3" + [(set (match_operand:TI 0 "register_operand" "=&d") + (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") + (match_operand:TI 2 "general_operand" "do") ) ) + (clobber (reg:CC 33))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(parallel + [(set (reg:CCL1 33) + (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) + (match_dup 7))) + (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) + (parallel + [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) + (ltu:DI (reg:CCL1 33) (const_int 0)))) + (clobber (reg:CC 33))])] + "operands[3] = operand_subword (operands[0], 0, 0, TImode); + operands[4] = operand_subword (operands[1], 0, 0, TImode); + operands[5] = operand_subword (operands[2], 0, 0, TImode); + operands[6] = operand_subword (operands[0], 1, 0, TImode); + operands[7] = operand_subword (operands[1], 1, 0, TImode); + operands[8] = operand_subword (operands[2], 1, 0, TImode);" + [(set_attr "op_type" "NN")]) + +; ; adddi3 instruction pattern(s). ; @@ -3826,6 +3855,35 @@ ;; ; +; subti3 instruction pattern(s). +; + +(define_insn_and_split "subti3" + [(set (match_operand:TI 0 "register_operand" "=&d") + (minus:TI (match_operand:TI 1 "register_operand" "0") + (match_operand:TI 2 "general_operand" "do") ) ) + (clobber (reg:CC 33))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(parallel + [(set (reg:CCL2 33) + (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) + (match_dup 7))) + (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) + (parallel + [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) + (gtu:DI (reg:CCL2 33) (const_int 0)))) + (clobber (reg:CC 33))])] + "operands[3] = operand_subword (operands[0], 0, 0, TImode); + operands[4] = operand_subword (operands[1], 0, 0, TImode); + operands[5] = operand_subword (operands[2], 0, 0, TImode); + operands[6] = operand_subword (operands[0], 1, 0, TImode); + operands[7] = operand_subword (operands[1], 1, 0, TImode); + operands[8] = operand_subword (operands[2], 1, 0, TImode);" + [(set_attr "op_type" "NN")]) + +; ; subdi3 instruction pattern(s). ; |