diff options
| author | krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-03-01 09:21:23 +0000 |
|---|---|---|
| committer | krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-03-01 09:21:23 +0000 |
| commit | 6191f2a0a9178047100b5b3977a473d62ea9f845 (patch) | |
| tree | 7e280c310a8ce6431854ec7979908ba61c019e32 /gcc/config/s390/s390.md | |
| parent | e84de992c1616aa1fb534ce3b9931e9313eb19d5 (diff) | |
| download | gcc-6191f2a0a9178047100b5b3977a473d62ea9f845.tar.gz | |
S/390: Get rid of Y constraint in rotate patterns.
This patch introduces substitution patterns to add PLUS const_int, and
AND operands to patterns and uses this to rewrite the existing rotate
pattern.
gcc/ChangeLog:
2016-03-01 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/predicates.md (const_int_6bitset_operand): New
predicates.
* config/s390/s390.md: Include subst.md.
("rotl<mode>3"): New expander.
("rotl<mode>3", "*rotl<mode>3_and"): Merge insn definitions into
...
("*rotl<mode>3<addr_style_op><masked_op>"): New insn definition.
* config/s390/subst.md: New file.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233843 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/s390/s390.md')
| -rw-r--r-- | gcc/config/s390/s390.md | 31 |
1 files changed, 14 insertions, 17 deletions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 65b6ce9085c..b7c037a5229 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -741,6 +741,8 @@ (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")]) +;; Subst pattern definitions +(include "subst.md") (include "vector.md") @@ -8376,28 +8378,23 @@ ; rotl(di|si)3 instruction pattern(s). ; -; rll, rllg -(define_insn "rotl<mode>3" - [(set (match_operand:GPR 0 "register_operand" "=d") - (rotate:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] +(define_expand "rotl<mode>3" + [(set (match_operand:GPR 0 "register_operand" "") + (rotate:GPR (match_operand:GPR 1 "register_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")))] "TARGET_CPU_ZARCH" - "rll<g>\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") - (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + "") ; rll, rllg -(define_insn "*rotl<mode>3_and" - [(set (match_operand:GPR 0 "register_operand" "=d") - (rotate:GPR (match_operand:GPR 1 "register_operand" "d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))))] - "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" - "rll<g>\t%0,%1,%Y2" +(define_insn "*rotl<mode>3<addr_style_op><masked_op>" + [(set (match_operand:GPR 0 "register_operand" "=d") + (rotate:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:SI 2 "nonmemory_operand" "an")))] + "TARGET_CPU_ZARCH" + "rll<g>\t%0,%1,<addr_style_op_ops>" [(set_attr "op_type" "RSE") (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + (set_attr "z10prop" "z10_super_E1")]) ;; |