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| author | krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-03-24 14:02:17 +0000 |
|---|---|---|
| committer | krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-03-24 14:02:17 +0000 |
| commit | d87bc45cc57660a7ab4bd539ce2bca97e7a6bb94 (patch) | |
| tree | 598e9a714c2b2515f8dfa7a17318f2d5e740e9e5 /gcc/config/s390/s390.md | |
| parent | bd97b7d007706034d52dd1f5299c228413bea330 (diff) | |
| download | gcc-d87bc45cc57660a7ab4bd539ce2bca97e7a6bb94.tar.gz | |
S/390: arch12: Add indirect branch pattern
This adds support for the branch indirect instruction.
gcc/ChangeLog:
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.md ("indirect_jump"): Turn insn definition into
expander.
("*indirect_jump", "*indirect2_jump"): New pattern definitions.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246456 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/s390/s390.md')
| -rw-r--r-- | gcc/config/s390/s390.md | 48 |
1 files changed, 37 insertions, 11 deletions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 53c8fed517c..32753ef746d 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -9509,20 +9509,46 @@ ; indirect-jump instruction pattern(s). ; -(define_insn "indirect_jump" - [(set (pc) (match_operand 0 "address_operand" "ZR"))] +(define_expand "indirect_jump" + [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] "" { - if (get_attr_op_type (insn) == OP_TYPE_RR) - return "br\t%0"; + if (address_operand (operands[0], GET_MODE (operands[0]))) + ; + else if (TARGET_ARCH12 + && GET_MODE (operands[0]) == Pmode + && memory_operand (operands[0], Pmode)) + ; else - return "b\t%a0"; -} - [(set (attr "op_type") - (if_then_else (match_operand 0 "register_operand" "") - (const_string "RR") (const_string "RX"))) - (set_attr "type" "branch") - (set_attr "atype" "agen")]) + operands[0] = force_reg (Pmode, operands[0]); +}) + +(define_insn "*indirect_jump" + [(set (pc) + (match_operand 0 "address_operand" "a,ZR"))] + "" + "@ + br\t%0 + b\t%a0" + [(set_attr "op_type" "RR,RX") + (set_attr "type" "branch") + (set_attr "atype" "agen") + (set_attr "cpu_facility" "*")]) + +; FIXME: LRA does not appear to be able to deal with MEMs being +; checked against address constraints like ZR above. So make this a +; separate pattern for now. +(define_insn "*indirect2_jump" + [(set (pc) + (match_operand 0 "nonimmediate_operand" "a,T"))] + "" + "@ + br\t%0 + bi\t%0" + [(set_attr "op_type" "RR,RXY") + (set_attr "type" "branch") + (set_attr "atype" "agen") + (set_attr "cpu_facility" "*,arch12")]) ; ; casesi instruction pattern(s). |