s390: Constraints, predicates, and op letters for contiguous bitmasks

        * config/s390/constraints.md (NxxDq, NxxSq): New.
        * config/s390/predicates.md (contiguous_bitmask_operand): New.
        * config/s390/s390.c (print_operand) ['e', 'f', 's', 't']: New
        operand letters.
        * config/s390/s390.md (bfstart, bfend): New mode attrs.
        (*insv<GPR>_zEC12_noshift): Use them.
        (*insv<GPR>_z10_noshift): Likewise.
        (*insv<GPR>_or_z10_noshift): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@194640 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 15 insertions, 59 deletions

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index bea58cd7a83..ee030ba43a4 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -527,6 +527,10 @@
 ;; Maximum unsigned integer that fits in MODE.
 (define_mode_attr max_uint [(HI "65535") (QI "255")])
 
+;; Start and end field computations for RISBG et al.
+(define_mode_attr bfstart [(DI "s") (SI "t")])
+(define_mode_attr bfend   [(DI "e") (SI "f")])
+
 ;;
 ;;- Compare instructions.
 ;;
@@ -3420,56 +3424,22 @@
 (define_insn "*insv<mode>_zEC12_noshift"
   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
 	(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
-			  (match_operand 2 "const_int_operand" "n"))
+			  (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
 		 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
-			  (match_operand 4 "const_int_operand" "n"))))]
-  "TARGET_ZEC12
-   && s390_contiguous_bitmask_p (INTVAL (operands[2]),
-                                 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
-   && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
-
-{
-  int start;
-  int size;
-
-  s390_contiguous_bitmask_p (INTVAL (operands[2]),
-                             GET_MODE_BITSIZE (<MODE>mode), &start, &size);
-
-  operands[5] = GEN_INT (64 - start - size); /* start bit position */
-  operands[6] = GEN_INT (64 - 1 - start);    /* end bit position */
-  operands[7] = const0_rtx;                  /* left shift count */
-
-  return "risbgn\t%0,%1,%b5,%b6,%b7";
-}
+			  (match_operand:GPR 4 "const_int_operand" ""))))]
+  "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
+  "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
   [(set_attr "op_type" "RIE")])
 
-; and op1 with a mask being 1 for the selected bits and 0 for the rest
-; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
 (define_insn "*insv<mode>_z10_noshift"
   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
 	(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
-			  (match_operand 2 "const_int_operand" "n"))
+			  (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
 		 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
-			  (match_operand 4 "const_int_operand" "n"))))
+			  (match_operand:GPR 4 "const_int_operand" ""))))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_Z10
-   && s390_contiguous_bitmask_p (INTVAL (operands[2]),
-                                 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
-   && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
-
-{
-  int start;
-  int size;
-
-  s390_contiguous_bitmask_p (INTVAL (operands[2]),
-                             GET_MODE_BITSIZE (<MODE>mode), &start, &size);
-
-  operands[5] = GEN_INT (64 - start - size); /* start bit position */
-  operands[6] = GEN_INT (64 - 1 - start);    /* end bit position */
-  operands[7] = const0_rtx;                  /* left shift count */
-
-  return "risbg\t%0,%1,%b5,%b6,%b7";
-}
+  "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
+  "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
 
@@ -3477,25 +3447,11 @@
 (define_insn "*insv<mode>_or_z10_noshift"
   [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
 	(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
-			  (match_operand 2 "const_int_operand" "n"))
+			  (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
 		(match_operand:GPR 3 "nonimmediate_operand" "0")))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_Z10
-   && s390_contiguous_bitmask_p (INTVAL (operands[2]),
-                                 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
-{
-  int start;
-  int size;
-
-  s390_contiguous_bitmask_p (INTVAL (operands[2]),
-                             GET_MODE_BITSIZE (<MODE>mode), &start, &size);
-
-  operands[4] = GEN_INT (64 - start - size); /* start bit position */
-  operands[5] = GEN_INT (64 - 1 - start);    /* end bit position */
-  operands[6] = const0_rtx;                  /* left shift count */
-
-  return "rosbg\t%0,%1,%b4,%b5,%b6";
-}
+  "TARGET_Z10"
+  "rosbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
   [(set_attr "op_type" "RIE")])
 
 (define_insn "*insv<mode>_mem_reg"