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authorvmakarov <vmakarov@138bc75d-0d04-0410-961f-82ee72b054a4>2011-03-28 01:53:24 +0000
committervmakarov <vmakarov@138bc75d-0d04-0410-961f-82ee72b054a4>2011-03-28 01:53:24 +0000
commita5af08d26ce1678e462f91bb3fb9336e30d02ca8 (patch)
tree761665b37aeeeb5eb4e3f9b4770772ea49679cc0 /gcc/config/s390/s390.h
parent24b0a129a158dc3987a676c625817b9b21e9d4e9 (diff)
downloadgcc-a5af08d26ce1678e462f91bb3fb9336e30d02ca8.tar.gz
2011-03-27 Vladimir Makarov <vmakarov@redhat.com>
PR bootstrap/48307 Revert the previous patch. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@171589 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/s390/s390.h')
-rw-r--r--gcc/config/s390/s390.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 8825ae224f4..c6ba4ff2453 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -468,6 +468,19 @@ enum reg_class
{ 0xffffffff, 0x0000003f }, /* ALL_REGS */ \
}
+/* The following macro defines cover classes for Integrated Register
+ Allocator. Cover classes is a set of non-intersected register
+ classes covering all hard registers used for register allocation
+ purpose. Any move between two registers of a cover class should be
+ cheaper than load or store of the registers. The macro value is
+ array of register classes with LIM_REG_CLASSES used as the end
+ marker. */
+
+#define IRA_COVER_CLASSES \
+{ \
+ GENERAL_REGS, FP_REGS, CC_REGS, ACCESS_REGS, LIM_REG_CLASSES \
+}
+
/* In some case register allocation order is not enough for IRA to
generate a good code. The following macro (if defined) increases
cost of REGNO for a pseudo approximately by pseudo usage frequency