diff options
| author | jsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-03-02 01:55:06 +0000 |
|---|---|---|
| committer | jsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4> | 2007-03-02 01:55:06 +0000 |
| commit | 114a8a4bd9b29f256ead5b126dff3f11b151fd4b (patch) | |
| tree | c1e2ef7127a2f1f85055feb6b8c5cb896632aad0 /gcc/config/rs6000 | |
| parent | 130effcad254850ce1a672d7a36aac3278671458 (diff) | |
| download | gcc-114a8a4bd9b29f256ead5b126dff3f11b151fd4b.tar.gz | |
* target.h (init_dwarf_reg_sizes_extra): New target hook.
* target-def.h (TARGET_INIT_DWARF_REG_SIZES_EXTRA): New default.
* doc/tm.texi (TARGET_INIT_DWARF_REG_SIZES_EXTRA): Document.
* dwarf2out.c (expand_builtin_init_dwarf_reg_sizes): Call this
hook.
* config/rs6000/rs6000.c (TARGET_INIT_DWARF_REG_SIZES_EXTRA,
rs6000_init_dwarf_reg_sizes_extra): New.
* config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Support
SPE register high parts.
testsuite:
* gcc.target/powerpc/spe-unwind-1.c, g++.dg/eh/simd-5.C: New
tests.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@122468 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000')
| -rw-r--r-- | gcc/config/rs6000/linux-unwind.h | 11 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 28 |
2 files changed, 39 insertions, 0 deletions
diff --git a/gcc/config/rs6000/linux-unwind.h b/gcc/config/rs6000/linux-unwind.h index 182bb6d9f34..b6262510a7b 100644 --- a/gcc/config/rs6000/linux-unwind.h +++ b/gcc/config/rs6000/linux-unwind.h @@ -301,6 +301,17 @@ ppc_fallback_frame_state (struct _Unwind_Context *context, fs->regs.reg[VRSAVE_REGNO].loc.offset = (long) &vregs->vsave - new_cfa; } + /* If we have SPE register high-parts... we check at compile-time to + avoid expanding the code for all other PowerPC. */ +#ifdef __SPE__ + for (i = 0; i < 32; i++) + { + fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET; + fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset + = (long) ®s->vregs - new_cfa + 4 * i; + } +#endif + return _URC_NO_REASON; } diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 7a61d6c4b6f..b9614b8ff27 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -765,6 +765,7 @@ static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); int easy_vector_constant (rtx, enum machine_mode); static bool rs6000_is_opaque_type (tree); static rtx rs6000_dwarf_register_span (rtx); +static void rs6000_init_dwarf_reg_sizes_extra (tree); static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; static rtx rs6000_tls_get_addr (void); @@ -1028,6 +1029,9 @@ static const char alt_reg_names[][8] = #undef TARGET_DWARF_REGISTER_SPAN #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span +#undef TARGET_INIT_DWARF_REG_SIZES_EXTRA +#define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra + /* On rs6000, function arguments are promoted, as are function return values. */ #undef TARGET_PROMOTE_FUNCTION_ARGS @@ -20657,6 +20661,30 @@ rs6000_dwarf_register_span (rtx reg) gen_rtx_REG (SImode, regno + 1200))); } +/* Fill in sizes for SPE register high parts in table used by unwinder. */ + +static void +rs6000_init_dwarf_reg_sizes_extra (tree address) +{ + if (TARGET_SPE) + { + int i; + enum machine_mode mode = TYPE_MODE (char_type_node); + rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0); + rtx mem = gen_rtx_MEM (BLKmode, addr); + rtx value = gen_int_mode (4, mode); + + for (i = 1201; i < 1232; i++) + { + int column = DWARF_REG_TO_UNWIND_COLUMN (i); + HOST_WIDE_INT offset + = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode); + + emit_move_insn (adjust_address (mem, mode, offset), value); + } + } +} + /* Map internal gcc register numbers to DWARF2 register numbers. */ unsigned int |