diff options
| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2010-11-08 19:02:35 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2010-11-08 19:02:35 +0000 |
| commit | f4becba81532699a3d4681460fb0107791901a58 (patch) | |
| tree | d3629a4484e52668a76669cedc55462f9bb04f45 /gcc/config/rs6000 | |
| parent | 5c5e8419ff673baff17839b5f5db91bfe1e1244f (diff) | |
| download | gcc-f4becba81532699a3d4681460fb0107791901a58.tar.gz | |
Fix PR 46378 and PR 45585
From-SVN: r166448
Diffstat (limited to 'gcc/config/rs6000')
| -rw-r--r-- | gcc/config/rs6000/darwin.md | 16 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 2 |
3 files changed, 16 insertions, 9 deletions
diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index 356b879b2a4..a61240a1f48 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -141,11 +141,13 @@ You should have received a copy of the GNU General Public License ;; 64-bit MachO load/store support (define_insn "movdi_low" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d") + (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") (match_operand 2 "" ""))))] "TARGET_MACHO && TARGET_64BIT" - "{l|ld} %0,lo16(%2)(%1)" + "@ + {l|ld} %0,lo16(%2)(%1) + lfd %0,lo16(%2)(%1)" [(set_attr "type" "load") (set_attr "length" "4")]) @@ -159,11 +161,13 @@ You should have received a copy of the GNU General Public License (set_attr "length" "4")]) (define_insn "movdi_low_st" - [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") + [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") (match_operand 2 "" ""))) - (match_operand:DI 0 "gpc_reg_operand" "r"))] + (match_operand:DI 0 "gpc_reg_operand" "r,*!d"))] "TARGET_MACHO && TARGET_64BIT" - "{st|std} %0,lo16(%2)(%1)" + "@ + {st|std} %0,lo16(%2)(%1) + stfd %0,lo16(%2)(%1)" [(set_attr "type" "store") (set_attr "length" "4")]) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 854f6d00f88..eadc1222c44 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2577,7 +2577,8 @@ rs6000_option_override_internal (const char *default_cpu) /* Masks for instructions set at various powerpc ISAs. */ enum { ISA_2_1_MASKS = MASK_MFCRF, - ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB | MASK_FPRND), + ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), + ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, @@ -2746,7 +2747,9 @@ rs6000_option_override_internal (const char *default_cpu) target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit); else if (TARGET_CMPB) target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit); - else if (TARGET_POPCNTB || TARGET_FPRND) + else if (TARGET_FPRND) + target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit); + else if (TARGET_POPCNTB) target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit); else if (TARGET_ALTIVEC) target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1dbf52c3c3d..37f5ad227b4 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7149,7 +7149,7 @@ (define_insn "*friz" [(set (match_operand:DF 0 "gpc_reg_operand" "=d") (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_POPCNTB + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ" "friz %0,%1" |