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| author | segher <segher@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-05-07 22:00:58 +0000 |
|---|---|---|
| committer | segher <segher@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-05-07 22:00:58 +0000 |
| commit | 631c977b56234aef7d6242d09924f5a0a081cc64 (patch) | |
| tree | cd8a170e4a1bf065792be21e8461f7608f25a897 /gcc/config/rs6000/vsx.md | |
| parent | a3ba513eef70417cc12a3cf01f8dc092162aa78b (diff) | |
| download | gcc-631c977b56234aef7d6242d09924f5a0a081cc64.tar.gz | |
rs6000: New attributes for load/store: "sign_extend", "update" and "indexed"
The new attributes replace the instruction types *_ext*, *_u, *_ux.
This simplifies all code that does not care about the addressing modes,
putting the burden on the code that does care (mostly the scheduling
descriptions for certain CPUs).
It fixes a few minor bugs in the process.
The "update" and "indexed" attributes are automatic for any insn that
has a MEM as operand 0 or 1. Other insns have to set it manually, if
they do not like the default (which is "no"). Insns that are type
load/store/fpload/fpstore but have fewer than two operands need to set
it too, or the compiler will crash. There are very few of those.
This tries not to change semantics anywhere; in particular, the string
and multiple instructions set both "update" and "indexed" (although
they are neither).
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210190 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/vsx.md')
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 33 |
1 files changed, 5 insertions, 28 deletions
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 23d85ab0628..cf430bb5387 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -657,8 +657,9 @@ gcc_unreachable (); } } - [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store_ux,store_ux,load_ux,load_ux, *, *") - (set_attr "length" " 4, 4, 4, 4, 8, 4, 4, 16, 16, 16, 16,16,16") + [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store,store,load,load, *, *") + (set_attr "update" " *, *, *, *, *, *, *, yes, yes, yes, yes, *, *") + (set_attr "length" " 4, 4, 4, 4, 8, 4, 4, 16, 16, 16, 16,16,16") (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING") (const_string "always") (const_string "conditional")))]) @@ -1613,22 +1614,7 @@ lfd%U1%X1 %0,%1 lxsd%U1x %x0,%y1 ld%U1%X1 %0,%1" - [(set_attr_alternative "type" - [(if_then_else - (match_test "update_indexed_address_mem (operands[1], VOIDmode)") - (const_string "fpload_ux") - (if_then_else - (match_test "update_address_mem (operands[1], VOIDmode)") - (const_string "fpload_u") - (const_string "fpload"))) - (const_string "fpload") - (if_then_else - (match_test "update_indexed_address_mem (operands[1], VOIDmode)") - (const_string "load_ux") - (if_then_else - (match_test "update_address_mem (operands[1], VOIDmode)") - (const_string "load_u") - (const_string "load")))]) + [(set_attr "type" "fpload,fpload,load") (set_attr "length" "4")]) ;; Optimize storing a single scalar element that is the right location to @@ -1643,16 +1629,7 @@ stfd%U0%X0 %1,%0 stxsd%U0x %x1,%y0 stxsd%U0x %x1,%y0" - [(set_attr_alternative "type" - [(if_then_else - (match_test "update_indexed_address_mem (operands[0], VOIDmode)") - (const_string "fpstore_ux") - (if_then_else - (match_test "update_address_mem (operands[0], VOIDmode)") - (const_string "fpstore_u") - (const_string "fpstore"))) - (const_string "fpstore") - (const_string "fpstore")]) + [(set_attr "type" "fpstore") (set_attr "length" "4")]) ;; Extract a SF element from V4SF |