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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2015-07-02 18:30:35 +0000 |
|---|---|---|
| committer | William Schmidt <wschmidt@gcc.gnu.org> | 2015-07-02 18:30:35 +0000 |
| commit | a05d02b293b299352b9523875e96bf697f96baf4 (patch) | |
| tree | bb03c3548e8fccec3bac8f76ce2b724f4cc72506 /gcc/config/rs6000/vector.md | |
| parent | 83eb71f4e4a081e25a5e953acfc8757c5f4e85fb (diff) | |
| download | gcc-a05d02b293b299352b9523875e96bf697f96baf4.tar.gz | |
rs6000-builtin.def (CMPGE_16QI): New built-in definition.
[gcc]
2015-07-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000-builtin.def (CMPGE_16QI): New built-in
definition.
(CMPGE_8HI): Likewise.
(CMPGE_4SI): Likewise.
(CMPGE_2DI): Likewise.
(CMPGE_U16QI): Likewise.
(CMPGE_U8HI): Likewise.
(CMPGE_U4SI): Likewise.
(CMPGE_U2DI): Likewise.
(CMPLE_16QI): Likewise.
(CMPLE_8HI): Likewise.
(CMPLE_4SI): Likewise.
(CMPLE_2DI): Likewise.
(CMPLE_U16QI): Likewise.
(CMPLE_U8HI): Likewise.
(CMPLE_U4SI): Likewise.
(CMPLE_U2DI): Likewise.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
overloads for ALTIVEC_BUILTIN_VEC_CMPGE and
ALTIVEC_BUILTIN_VEC_CMPLE.
* config/rs6000/vector.md (vector_ge<mode>): Restrict to
floating-point vector modes.
(vector_nlt<mode>): New define_expand.
(vector_nltu<mode>): Likewise.
(vector_ngt<mode>): Likewise.
(vector_ngtu<mode>): Likewise.
[gcc/testsuite]
2015-07-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.target/powerpc/vec-cmp.c: New test.
From-SVN: r225351
Diffstat (limited to 'gcc/config/rs6000/vector.md')
| -rw-r--r-- | gcc/config/rs6000/vector.md | 57 |
1 files changed, 54 insertions, 3 deletions
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 27be1609acf..40d596b4381 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -446,12 +446,25 @@ "") (define_expand "vector_ge<mode>" - [(set (match_operand:VEC_C 0 "vlogical_operand" "") - (ge:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "") - (match_operand:VEC_C 2 "vlogical_operand" "")))] + [(set (match_operand:VEC_F 0 "vlogical_operand" "") + (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand" "") + (match_operand:VEC_F 2 "vlogical_operand" "")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") +; >= for integer vectors: swap operands and apply not-greater-than +(define_expand "vector_nlt<mode>" + [(set (match_operand:VEC_I 3 "vlogical_operand" "") + (gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "") + (match_operand:VEC_I 1 "vlogical_operand" ""))) + (set (match_operand:VEC_I 0 "vlogical_operand" "") + (not:VEC_I (match_dup 3)))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" + " +{ + operands[3] = gen_reg_rtx_and_attrs (operands[0]); +}") + (define_expand "vector_gtu<mode>" [(set (match_operand:VEC_I 0 "vint_operand" "") (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "") @@ -459,6 +472,19 @@ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") +; >= for integer vectors: swap operands and apply not-greater-than +(define_expand "vector_nltu<mode>" + [(set (match_operand:VEC_I 3 "vlogical_operand" "") + (gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "") + (match_operand:VEC_I 1 "vlogical_operand" ""))) + (set (match_operand:VEC_I 0 "vlogical_operand" "") + (not:VEC_I (match_dup 3)))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" + " +{ + operands[3] = gen_reg_rtx_and_attrs (operands[0]); +}") + (define_expand "vector_geu<mode>" [(set (match_operand:VEC_I 0 "vint_operand" "") (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "") @@ -466,6 +492,31 @@ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") +; <= for integer vectors: apply not-greater-than +(define_expand "vector_ngt<mode>" + [(set (match_operand:VEC_I 3 "vlogical_operand" "") + (gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "") + (match_operand:VEC_I 2 "vlogical_operand" ""))) + (set (match_operand:VEC_I 0 "vlogical_operand" "") + (not:VEC_I (match_dup 3)))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" + " +{ + operands[3] = gen_reg_rtx_and_attrs (operands[0]); +}") + +(define_expand "vector_ngtu<mode>" + [(set (match_operand:VEC_I 3 "vlogical_operand" "") + (gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "") + (match_operand:VEC_I 2 "vlogical_operand" ""))) + (set (match_operand:VEC_I 0 "vlogical_operand" "") + (not:VEC_I (match_dup 3)))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" + " +{ + operands[3] = gen_reg_rtx_and_attrs (operands[0]); +}") + (define_insn_and_split "*vector_uneq<mode>" [(set (match_operand:VEC_F 0 "vfloat_operand" "") (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") |