Merge branch 'master' into gcn

1 files changed, 16 insertions, 14 deletions

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index dedb2e3c193..f78dbf913ec 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -690,7 +690,9 @@
 ;; Iterator to optimize the following cases:
 ;;	D-form load to FPR register & move to Altivec register
 ;;	Move Altivec register to FPR register and store
-(define_mode_iterator ALTIVEC_DFORM [DI DF SF])
+(define_mode_iterator ALTIVEC_DFORM [DF
+				     SF
+				     (DI "TARGET_POWERPC64")])
 
 
 ;; Start with fixed-point load and store insns.  Here we put only the more
@@ -1631,7 +1633,7 @@
 
       /* Adding a constant to r0 is not a valid insn, so use a different
 	 strategy in that case.  */
-      if (REGNO (operands[1]) == 0 || REGNO (tmp) == 0)
+      if (reg_or_subregno (operands[1]) == 0 || reg_or_subregno (tmp) == 0)
 	{
 	  if (operands[0] == operands[1])
 	    FAIL;
@@ -7391,8 +7393,8 @@
 ;; except for 0.0 which can be created on VSX with an xor instruction.
 
 (define_insn "*mov<mode>_hardfloat32"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_p9>,wY,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
-	(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,wY,<f64_p9>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
+	(match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT 
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7400,10 +7402,10 @@
    stfd%U0%X0 %1,%0
    lfd%U1%X1 %0,%1
    fmr %0,%1
-   lxsd%U1x %x0,%y1
-   stxsd%U0x %x1,%y0
    lxsd %0,%1
    stxsd %1,%0
+   lxsd%U1x %x0,%y1
+   stxsd%U0x %x1,%y0
    xxlor %x0,%x1,%x1
    xxlxor %x0,%x0,%x0
    #
@@ -13967,13 +13969,13 @@
 ;;	LXSDX 32,3,9
 
 (define_peephole2
-  [(match_scratch:DI 0 "b")
+  [(match_scratch:P 0 "b")
    (set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand")
 	(match_operand:ALTIVEC_DFORM 2 "simple_offsettable_mem_operand"))
    (set (match_operand:ALTIVEC_DFORM 3 "altivec_register_operand")
 	(match_dup 1))]
-  "TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_<MODE>
-   && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
+  "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
+   && peep2_reg_dead_p (2, operands[1])"
   [(set (match_dup 0)
 	(match_dup 4))
    (set (match_dup 3)
@@ -13988,7 +13990,7 @@
   add_op0 = XEXP (addr, 0);
   add_op1 = XEXP (addr, 1);
   gcc_assert (REG_P (add_op0));
-  new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg);
+  new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
 
   operands[4] = add_op1;
   operands[5] = change_address (mem, <MODE>mode, new_addr);
@@ -14004,13 +14006,13 @@
 ;;	STXSDX 32,3,9
 
 (define_peephole2
-  [(match_scratch:DI 0 "b")
+  [(match_scratch:P 0 "b")
    (set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand")
 	(match_operand:ALTIVEC_DFORM 2 "altivec_register_operand"))
    (set (match_operand:ALTIVEC_DFORM 3 "simple_offsettable_mem_operand")
 	(match_dup 1))]
-  "TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_<MODE>
-   && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
+  "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
+   && peep2_reg_dead_p (2, operands[1])"
   [(set (match_dup 0)
 	(match_dup 4))
    (set (match_dup 5)
@@ -14025,7 +14027,7 @@
   add_op0 = XEXP (addr, 0);
   add_op1 = XEXP (addr, 1);
   gcc_assert (REG_P (add_op0));
-  new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg);
+  new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
 
   operands[4] = add_op1;
   operands[5] = change_address (mem, <MODE>mode, new_addr);